Download
variables attributes functions and procedures data types n.
Skip this Video
Loading SlideShow in 5 Seconds..
Variables, Attributes, Functions and Procedures, Data Types PowerPoint Presentation
Download Presentation
Variables, Attributes, Functions and Procedures, Data Types

Variables, Attributes, Functions and Procedures, Data Types

219 Vues Download Presentation
Télécharger la présentation

Variables, Attributes, Functions and Procedures, Data Types

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. ECE 545 Lecture 10 Variables, Attributes,Functions and Procedures,Data Types ECE 545 – Introduction to VHDL

  2. Resources • Volnei A. Pedroni,Circuit Design with VHDL • Chapter 7, Signals and Variables • Chapter 11, Functions and Procedures • Sundar Rajan, Essential VHDL: RTL Synthesis • Done Right • Chapter 11, Scalable and Parameterizable • Design • Chapter 12, Enhancing Design Readability • and Reuse ECE 545 – Introduction to VHDL

  3. Combinational Logic Synthesis for Intermediates ECE 545 – Introduction to VHDL

  4. 2-to-4 Decoder w y 0 0 w y 1 1 y 2 y En 3 w w y y y y En 1 0 0 1 2 3 0 0 0 1 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 1 0 1 1 1 0 0 0 1 x x 0 0 0 0 0 (a) Truth table (b) Graphical symbol ECE 545 – Introduction to VHDL

  5. VHDL code for a 2-to-4 Decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END dec2to4 ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= “0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", “1000" WHEN "111", "0000" WHEN OTHERS ; END dataflow ; ECE 545 – Introduction to VHDL

  6. Describing combinational logic using processes LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS BEGIN PROCESS ( w, En ) BEGIN IF En = '1' THEN CASE w IS WHEN "00" => y <= "1000" ; WHEN "01" => y <= "0100" ; WHEN "10" => y <= "0010" ; WHEN OTHERS => y <= "0001" ; END CASE ; ELSE y <= "0000" ; END IF ; END PROCESS ; END Behavior ; ECE 545 – Introduction to VHDL

  7. Describing combinational logic using processes LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY seg7 IS PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ; END seg7 ; ARCHITECTURE Behavior OF seg7 IS BEGIN PROCESS ( bcd ) BEGIN CASE bcd IS -- abcdefg WHEN "0000" => leds <= "1111110" ; WHEN "0001" => leds <= "0110000" ; WHEN "0010" => leds <= "1101101" ; WHEN "0011" => leds <= "1111001" ; WHEN "0100" => leds <= "0110011" ; WHEN "0101" => leds <= "1011011" ; WHEN "0110" => leds <= "1011111" ; WHEN "0111" => leds <= "1110000" ; WHEN "1000" => leds <= "1111111" ; WHEN "1001" => leds <= "1110011" ; WHEN OTHERS => leds <= "-------" ; END CASE ; END PROCESS ; END Behavior ; ECE 545 – Introduction to VHDL

  8. Describing combinational logic using processes LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY compare1 IS PORT ( A, B : IN STD_LOGIC ; AeqB : OUT STD_LOGIC ) ; END compare1 ; ARCHITECTURE Behavior OF compare1 IS BEGIN PROCESS ( A, B ) BEGIN AeqB <= '0' ; IF A = B THEN AeqB <= '1' ; END IF ; END PROCESS ; END Behavior ; ECE 545 – Introduction to VHDL

  9. Incorrect code for combinational logic- Implied latch (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY implied IS PORT ( A, B : IN STD_LOGIC ; AeqB : OUT STD_LOGIC ) ; END implied ; ARCHITECTURE Behavior OF implied IS BEGIN PROCESS ( A, B ) BEGIN IF A = B THEN AeqB <= '1' ; END IF ; END PROCESS ; END Behavior ; ECE 545 – Introduction to VHDL

  10. Incorrect code for combinational logic- Implied latch (2) A AeqB B ECE 545 – Introduction to VHDL

  11. Describing combinational logic using processes Rules that need to be followed: • All inputs to the combinational circuit should be included • in the sensitivity list • No other signals should be included • in the sensitivity list • None of the statements within the process • should be sensitive to rising or falling edges • All possible cases need to be covered in the internal • IF and CASE statements in order to avoid • implied latches ECE 545 – Introduction to VHDL

  12. Covering all cases in the IF statement Using ELSE IF A = B THEN AeqB <= '1' ; ELSE AeqB <= '0' ; Using default values AeqB <= '0' ; IF A = B THEN AeqB <= '1' ; ECE 545 – Introduction to VHDL

  13. Covering all cases in the CASE statement Using WHEN OTHERS CASE y IS WHEN S1 => Z <= "10"; WHEN S2 => Z <= "01"; WHEN S3 => Z <= "00"; WHEN OTHERS => Z <= „--"; END CASE; CASE y IS WHEN S1 => Z <= "10"; WHEN S2 => Z <= "01"; WHEN OTHERS => Z <= "00"; END CASE; Using default values Z <= "00"; CASE y IS WHEN S1 => Z <= "10"; WHEN S2 => Z <= "10"; END CASE; ECE 545 – Introduction to VHDL

  14. Combinational Logic Synthesis for Advanced ECE 545 – Introduction to VHDL

  15. Advanced VHDL for synthesis For complex, generic, and/or regular circuits you may consider using PROCESSES with internal VARIABLES and FOR LOOPs ECE 545 – Introduction to VHDL

  16. Variables ECE 545 – Introduction to VHDL

  17. Variable – Example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Numbits IS PORT ( X : IN STD_LOGIC_VECTOR(1 TO 3) ; Count : OUT INTEGER RANGE 0 TO 3) ; END Numbits ; ECE 545 – Introduction to VHDL

  18. Variable – Example (2) ARCHITECTURE Behavior OF Numbits IS BEGIN PROCESS(X) – count the number of bits in X equal to 1 VARIABLE Tmp: INTEGER; BEGIN Tmp := 0; FOR i IN 1 TO 3 LOOP IF X(i) = ‘1’ THEN Tmp := Tmp + 1; END IF; END LOOP; Count <= Tmp; END PROCESS; END Behavior ; ECE 545 – Introduction to VHDL

  19. Variables - features • Can only be declared within processes and subprograms (functions & procedures) • Initial value can be explicitly specified in the declaration • When assigned take an assigned value immediately • Variable assignments represent the desired behavior, not the structure of the circuit • Should be avoided, or at least used with caution in a synthesizable code ECE 545 – Introduction to VHDL

  20. Variables vs. Signals ECE 545 – Introduction to VHDL

  21. Variable – Example ARCHITECTURE Behavior OF Numbits IS BEGIN PROCESS(X) – count the number of bits in X equal to 1 VARIABLE Tmp: INTEGER; BEGIN Tmp := 0; FOR i IN 1 TO 3 LOOP IF X(i) = ‘1’ THEN Tmp := Tmp + 1; END IF; END LOOP; Count <= Tmp; END PROCESS; END Behavior ; ECE 545 – Introduction to VHDL

  22. Incorrect Code using Signals ARCHITECTURE Behavior OF Numbits IS SIGNAL Tmp : INTEGER RANGE 0 TO 3 ; BEGIN PROCESS(X) – count the number of bits in X equal to 1 BEGIN Tmp <= 0; FOR i IN 1 TO 3 LOOP IF X(i) = ‘1’ THEN Tmp <= Tmp + 1; END IF; END LOOP; Count <= Tmp; END PROCESS; END Behavior ; ECE 545 – Introduction to VHDL

  23. N-bit NAND LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY NANDn IS GENERIC (n: INTEGER := 8) PORT ( X : IN STD_LOGIC_VECTOR(1 TO n); Y : OUT STD_LOGIC); END NANDn; ECE 545 – Introduction to VHDL

  24. N-bit NAND architecture using variables ARCHITECTUREbehavioral1OFNANDnIS BEGIN PROCESS (X) VARIABLETmp: STD_LOGIC; BEGIN Tmp:=X(1); AND_bits: FOR i IN2TO n LOOP Tmp:=TmpANDX( i ) ; END LOOP AND_bits ; Y <= NOT Tmp ; END PROCESS; ENDbehavioral1 ; ECE 545 – Introduction to VHDL

  25. Incorrect N-bit NAND architecture using signals ARCHITECTUREbehavioral2OFNANDnIS SIGNALTmp: STD_LOGIC; BEGIN PROCESS (X) BEGIN Tmp<= X(1); AND_bits: FOR i IN2TO nLOOP Tmp<= TmpANDX( i ) ; END LOOP AND_bits ; Y <= NOT Tmp ; END PROCESS; ENDbehavioral2 ; ECE 545 – Introduction to VHDL

  26. Correct N-bit NAND architecture using signals ARCHITECTUREdataflow1 OFNANDnIS SIGNALTmp: STD_LOGIC_VECTOR(1 TO n); BEGIN Tmp(1)<= X(1); AND_bits: FOR i IN2TO n GENERATE Tmp(i)<= Tmp(i-1)ANDX( i ) ; END LOOP AND_bits ; Y <= NOT Tmp(n) ; ENDdataflow1 ; ECE 545 – Introduction to VHDL

  27. Correct N-bit NAND architecture using signals ARCHITECTUREdataflow2OFNANDnIS SIGNALTmp: STD_LOGIC_VECTOR(1 TO n); BEGIN Tmp <= (OTHERS => 1); Y <= ‘0’ WHEN X = Tmp ELSE ‘1’; ENDdataflow2 ; ECE 545 – Introduction to VHDL

  28. Parity generator entity LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY oddParityLoop IS GENERIC ( width : INTEGER := 8 ); PORT (ad : in STD_LOGIC_VECTOR (width - 1 DOWNTO 0); oddParity : out STD_LOGIC ) ; END oddParityLoop ; ECE 545 – Introduction to VHDL

  29. Parity generator architecture using signals ARCHITECTURE dataflow OF oddParityGen IS SIGNAL genXor: STD_LOGIC_VECTOR(width DOWNTO 0); BEGIN genXor(0) <= '0'; parTree: FOR i IN 1 TO width GENERATE genXor(i) <= genXor(i - 1) XOR ad(i - 1); END GENERATE; oddParity <= genXor(width) ; END dataflow ; ECE 545 – Introduction to VHDL

  30. Parity generator architecture using variables ARCHITECTURE behavioral OF oddParityLoop IS BEGIN PROCESS (ad) VARIABLE loopXor: STD_LOGIC; BEGIN loopXor := '0'; FOR i IN 0 to width -1 LOOP loopXor := loopXor XOR ad( i ) ; END LOOP ; oddParity <= loopXor ; END PROCESS; END behavioral ; ECE 545 – Introduction to VHDL

  31. Sequential Logic Synthesis for Beginners ECE 545 – Introduction to VHDL

  32. For Beginners Use processes with very simple structure only to describe - registers - shift registers - counters - state machines. Use examples discussed in class as a template. Create generic entities for registers, shift registers, and counters, and instantiate the corresponding components in a higher level circuit using GENERIC MAP PORT MAP. Supplement sequential components with combinational logic described using concurrent statements. ECE 545 – Introduction to VHDL

  33. Sequential Logic Synthesis for Intermediates ECE 545 – Introduction to VHDL

  34. For Intermmediates • Use Processes with IF and CASE statements only. Do not use LOOPS or VARIABLES. • Sensitivity list of the PROCESS should include only signals that can by themsleves change the outputs of the sequential circuit (typically, clock and asynchronous set or reset) • Do not use PROCESSes without sensitivity list (they can be synthesizable, but make simulation inefficient) ECE 545 – Introduction to VHDL

  35. Constrained Array Types ECE 545 – Introduction to VHDL

  36. One-dimensional arrays – Examples (1) type word_asc isarray(0 to 31) of std_logic; type word_desc is array(31 downto 0) ofstd_logic; ….. signal buffer_register: word_desc; ….. buffer_register(6) <= ‘1’; ….. variable tmp : word_asc; ….. tmp(5):= ‘0’; ECE 545 – Introduction to VHDL

  37. One-dimensional arrays – Examples (2) type controller_state is (initial, idle, active, error); type state_counts_imp is array(idle to error) of natural; type state_counts_exp is array(controller_state range idle to error) of natural; type state_counts_full is array(controller_state) of natural; ….. variable counters: state_counts_exp; ….. counters(active) := 0; ….. counters(active) := counters(active) + 1; ECE 545 – Introduction to VHDL

  38. Unconstrained Array Types ECE 545 – Introduction to VHDL

  39. Predefined Unconstrained Array Types Predefined bit_vector array of bits string array of characters Defined in the ieee.std_logic_1164 package: std_logic_vector array of std_logic_vectors ECE 545 – Introduction to VHDL

  40. Predefined Unconstrained Array Types subtype byte is bit_vector(7 downto 0); …. variable channel_busy : bit_vector(1 to 4); …. constant ready_message :string := “ready”; …. signal memory_bus: std_logic_vector (31 downto 0); ECE 545 – Introduction to VHDL

  41. User-defined Unconstrained Array Types type sample is array (natural range <>) of integer; …. variable long_sample is sample(0 to 255); …. constant look_up_table_1: sample := (127, -45, 63, 23, 76); …. ECE 545 – Introduction to VHDL

  42. Attributes of Arrays and Array Types ECE 545 – Introduction to VHDL

  43. Array Attributes A’left(N) left bound of index range of dimension N of A A’right(N) right bound of index range of dimension N of A A’low(N) lower bound of index range of dimension N of A A’high(N) upper bound of index range of dimension N of A A’range(N) index range of dimension N of A A’reverse_range(N) reversed index range of dimension N of A A’length(N) length of index range of dimension N of A A’ascending(N)true if index range of dimension N of A is an ascending range, false otherwise ECE 545 – Introduction to VHDL

  44. Array Attributes - Examples type A is array (1 to 4, 31 downto 0); A’left(1) = 1 A’right(2) = 0 A’low(1) = 1 A’high(2) = 31 A’range(1) = 1 to 4 A’length(2) = 32 A’ascending(2) = false ECE 545 – Introduction to VHDL

  45. Subprograms ECE 545 – Introduction to VHDL

  46. Subprograms • Include functions and procedures • Commonly used pieces of code • Can be placed in a library, and then reused and shared among various projects • Abstract operations that are repeatedly performed • Type conversions • Use only sequential statements, the same as processes ECE 545 – Introduction to VHDL

  47. Typical locations of subprograms PACKAGE PACKAGE BODY LIBRARY global ENTITY FUNCTION / PROCEDURE local for all architectures of a given entity ARCHITECTURE Declarative part local for a given architecture ECE 545 – Introduction to VHDL

  48. Functions ECE 545 – Introduction to VHDL

  49. Functions – basic features Functions • always return a single value as a result • Are called using formal and actual parametersthe same way as components • never modify parameters passed to them • parameters can only be constants (including generics) and signals (including ports); variables are not allowed; the default is a CONSTANT • when passing parameters, no range specification should be included (for example no RANGE for INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR) • are always used in some expression, and not called on their own ECE 545 – Introduction to VHDL

  50. Function syntax FUNCTION function_name (<parameter_list>) RETURN data_type IS [declarations] BEGIN (sequential statements) END function_name; ECE 545 – Introduction to VHDL