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Testing Semiconductor Memories

Testing Semiconductor Memories. Cheng-Wen Wu 吳誠文. Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University. Outline. Introduction RAM functional fault models and test algorithms RAM fault-coverage analysis Cocktail-March for testing word-oriented memories

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Testing Semiconductor Memories

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  1. Testing Semiconductor Memories Cheng-Wen Wu 吳誠文 Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University

  2. Outline • Introduction • RAM functional fault models and test algorithms • RAM fault-coverage analysis • Cocktail-March for testing word-oriented memories • Testing multi-port RAMs • Testing CAMs • Testing flash memories Cheng-Wen Wu, NTHU

  3. Introduction • Memory testing is a more and more important issue • RAMs are key components for electronic systems • Memories represent about 30% of the semiconductor market • Embedded memories aredominating the chip yield • Memory testing is more and more difficult • Growing density, capacity, and speed • Emerging new architecturesand technologies • Embedded memories: access, diagnostics & repair, heterogeneity, custom design, power & noise, scheduling, compression, etc. • Cost drives the need for more efficient test methodologies • IFA, fault modeling and simulation, test algorithm development and evaluation,diagnostics, DFT, BIST, BIRA, BISR, etc. • Test automation is required • Failure analysis, fault simulation, ATG, and diagnostics • BIST/BIRA/BISR generation Cheng-Wen Wu, NTHU

  4. Laser Repair Packaging Full Probe Test Marking Post-BI Test Burn-In (BI) Pre-BI Test Final Test QA Sample Test Visual Inspection Shipping Typical RAM Production Flow Wafer Cheng-Wen Wu, NTHU

  5. Scope of RAM Testing • Parametric Test: DC & AC • Reliability Screening • Long-cycle testing • Burn-in: static & dynamic BI • Functional Test • Device characterization • Failure analysis • Fault modeling • Simple but effective (accurate & realistic?) • Test algorithm generation • Small number of test patterns (data backgrounds) • High fault coverage • Short test time Cheng-Wen Wu, NTHU

  6. RAM Models • Behavior Level • Verilog/VHDL • Function Level • Verilog/VHDL/Block diagram • Normally not synthesizable • Circuit Level • Spice/Schematic • Layout Level • GDS-II/Geometry • Who should provide the model? Cheng-Wen Wu, NTHU

  7. Memory Function Model Example Cheng-Wen Wu, NTHU

  8. RAM Fault Models (Static) • Address-Decoder Fault (AF) • No cell accessed by certain address • Multiple cells accessed by certain address • Certain cell not accessed by any address • Certain cell accessed by multiple addresses • Stuck-At Fault (SAF) • Cell (line) SA0 or SA1 • Transition Fault (TF) • Cell fails to transit from 0 to 1 or 1 to 0 Cheng-Wen Wu, NTHU

  9. RAM Fault Models (Static) • Bridging Fault (BF) • Short between cells • AND type or OR type • Stuck-Open Fault (SOF) • Cell not accessible due to broken line • Neighborhood Pattern Sensitive Fault (NPSF) • Active (Dynamic) NPSF • Passive NPSF • Static NPSF Cheng-Wen Wu, NTHU

  10. RAM Fault Models (Static) • Coupling Fault (CF) • State Coupling Fault (CFst) • Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in given state • Inversion Coupling Fault (CFin) • Transition in coupling cell complements (inverts) coupled cell • Idempotent Coupling Fault (CFid) • Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to 0 Cheng-Wen Wu, NTHU

  11. RAM Fault Models (Dynamic) • Recovery Fault (RF) • Sense Amplifier Recovery Fault (SARF) • Sense amp saturation after reading/writing long run of 0 or 1 • Write Recovery Fault (WRF) • Write followed by reading/writing at different location resulting in reading/writing at same location • Write-after-write recovery fault • Read-after-write recovery fault • Results in functional faults---detected at high speed (e.g., GALROW/GALCOL) • Disturb Fault (DF) • Victim cell forced to 0 or 1 if we read or write aggressor cell (may be the same cell) Cheng-Wen Wu, NTHU

  12. RAM Fault Models (Dynamic) • Data Retention Fault (DRF) • DRAM • Refresh Fault • Refresh-Line Stuck-At Fault • Leakage Fault • Sleeping Sickness---loose data in less than specified hold time (typically tens of ms) • SRAM • Leakage Fault • Static Data Losses---defective pull-up • Checkerboard pattern triggers max leakage • BIST good for sync with refresh mechanism Cheng-Wen Wu, NTHU

  13. Test Time Complexity (100MHz) Cheng-Wen Wu, NTHU

  14. RAM Test Algorithm • A test algorithm (or simply test) is a finite sequence of test elements • A test element contains a number of memory operations (access commands) • Data pattern (background) specified for the Read operation • Address (sequence) specified for the Read and Write operations • A march test algorithm is a finite sequence of march elements • A march element is specified by an address order and a number of Read/Write operations Cheng-Wen Wu, NTHU

  15. Classical Test Algorithms • Zero-One Algorithm [Breuer & Friedman 1976] • Also known as MSCAN • For SAF • Solid background (pattern) • Complexity is 4N Cheng-Wen Wu, NTHU

  16. Classical Test Algorithms • Checkerboard Algorithm • Zero-one algorithm with checkerboard pattern • Complexity is 4N • For SAF and DRF Cheng-Wen Wu, NTHU

  17. Classical Test Algorithms • GallopingPattern (GALPAT) • Complexity is 4N**2---only for characterization • All AFs,TFs, CFs, and SAFs are located 1. Write background 0; 2. For BC = 0 to N-1 { Complement BC; For OC = 0 to N-1, OC != BC; { Read BC; Read OC; } Complement BC; } 3. Write background 1; 4. Repeat Step 2; Cheng-Wen Wu, NTHU

  18. Classical Test Algorithms • Sliding (Galloping) Row/Column/Diagonal • Based on GALPAT, but instead of a bit, a complete row, column, or diagonal is shifted • Complexity is 4N**1.5 Cheng-Wen Wu, NTHU

  19. Classical Test Algorithms • Butterfly Algorithm • Complexity is 5NlogN 1. Write background 0; 2. For BC = 0 to N-1 { Complement BC; dist = 1; While dist <= mdist /* mdist < 0.5 col/row length */ { Read cell @ dist north from BC; Read cell @ dist east from BC; Read cell @ dist south from BC; Read cell @ dist west from BC; Read BC; dist *= 2; } Complement BC; } 3. Write background 1; repeat Step 2; Cheng-Wen Wu, NTHU

  20. Classical Test Algorithms • Moving Inversion (MOVI) Algorithm [De Jonge & Smeulders 1976] • For functional and AC parametric test • Functional (13N): for AF, SAF, TF, and most CF • Parametric (12NlogN): for Read access time • 2 successive Reads @ 2 different addresses with different data for all 2-address sequences differing in 1 bit • Repeat T2~T5 for each address bit • GALPAT---all 2-address sequences Cheng-Wen Wu, NTHU

  21. 1 0 0 0 1 Classical Test Algorithms • Surround Disturb Algorithm • Examine how the cells in a row are affected when complementary data are written into adjacent cells of neighboring rows 1. For each cell[p,q] /* row p and column q */ { Write 0 in cell[p,q-1]; Write 0 in cell[p,q]; Write 0 in cell[p,q+1]; Write 1 in cell[p-1,q]; Read 0 from cell[p,q+1]; Write 1 in cell[p+1,q]; Read 0 from cell[p,q-1]; Read 0 from cell[p,q]; } 2. Repeat Step 1 with complementary data; Cheng-Wen Wu, NTHU

  22. Classical Test Algorithms • Zero-one and checkerboard algorithms do not have sufficient coverage • Other algorithms are too time-consuming for large RAM • Test time is the key factor of test cost • Complexity ranges from N2 to NlogN • Need linear-time test algorithms with small constants • March test algorithms Cheng-Wen Wu, NTHU

  23. March Tests • Zero-One (MSCAN) • Modified Algorithmic Test Sequence (MATS) [Nair, Thatte & Abraham 1979] • OR-type address decoder fault • AND-type address decoder fault • MATS+ [Abadir & Reghbati 1983] • For both OR- & AND-type AFs and SAF Cheng-Wen Wu, NTHU

  24. March Tests • Marching 1/0 [Breuer & Friedman 1976] • For AF, SAF, and TF • MATS++ [Goor 1991] • Also for AF, SAF, and TF • Complete and irredundant Cheng-Wen Wu, NTHU

  25. March Tests • March X • For AF, SAF, TF, & CFin • March C [Marinescu 1982] • For AF, SAF, TF, & all CFs---redundant • March C- [Goor 1991] • Also for AF, SAF, TF, & all CFs---irredundant Cheng-Wen Wu, NTHU

  26. March Tests • Limitations • Sequential faults in address decoders • RF • NPSF • (9N-2) for 2-CF [Marinescu 1982] • (2NlogN+11N) for 3-CF [Cockburn 1994] • Solutions • Address sequence variation • Hopping • Pseudorandom Cheng-Wen Wu, NTHU

  27. Coverage of March Tests • Extended March C- (11N) has a 100% coverage of SOF Cheng-Wen Wu, NTHU

  28. Testing Word-Oriented RAM • Background bit is replaced by background word • MATS++: • Conventional method is to use logm+1 different backgrounds for m-bit words • m=8: 00000000, 01010101, 00110011, and 00001111 • Apply the test algorithm logm+1=4 times, so complexity is 4*6N/8=3N Cheng-Wen Wu, NTHU

  29. Cocktail-March Algorithms • Motivation: • Repeating the same algorithm for all logm+1 backgrounds has redundancy • Different algorithm targets different faults • Approach: • Use multiple backgrounds in a single algorithm run • Merge and forge different algorithms and backgrounds into a single algorithm • Good for word-oriented memories Cheng-Wen Wu, NTHU

  30. March-CW • Algorithm: • March C- for solid background (0000) • Then a 5N March for each of other standard backgrounds (0101, 0011): • Result: • Complexity is (10+5logW)N, where W is word length and N is word count • Test time is reduced by 39% if W=4, as compared with extended March C- • Improvement increases as W increases Cheng-Wen Wu, NTHU

  31. Comparison (Full Coverage) Cheng-Wen Wu, NTHU

  32. Testing NPSF • NPSF test approaches • Tiling • Multi-background march • Easy BIST implementation • 5-cell neighborhood Cheng-Wen Wu, NTHU

  33. NPSF Models • Static NPSF (SNPSF) • BC forced to a certain state due to a certain deleted neighborhood (DN) pattern • Passive NPSF (PNPSF) • BC frozen due to a certain DN pattern • Active NPSF (ANPSF) • BC content changes due to a change in DN pattern • Change: a transition in one DN cell, with other DN cells & BC containing a certain pattern • Assumptions: • Single NPSF • Address scramble table is available • Memory is bit-oriented • Word-oriented memory is tested as multiple bit-oriented ones Cheng-Wen Wu, NTHU

  34. Test Strategy • Multi-Background March • To generate all neighborhood patterns Solid BG (FC < 30%) Another BG Cheng-Wen Wu, NTHU

  35. Testing PNPSF • March 17N: Cheng-Wen Wu, NTHU

  36. Data Background Generation • Data backgrounds • BG1: all zero • BG2: Ar[0], LSB of row address • BG3: Ar[1], second bit of row address • BG4: Ar[0]Ar[1] Cheng-Wen Wu, NTHU

  37. Testing ANPSF • March 12N: Cheng-Wen Wu, NTHU

  38. Time Complexity • 12 N/BG X 8 BG = 96N • Detects all NPSFs Cheng-Wen Wu, NTHU

  39. Multi-Port Memories • Popular architectures • k-port (k > 1) • n-read-1-write • FIFO Cheng-Wen Wu, NTHU

  40. 2-Port Topology Cheng-Wen Wu, NTHU

  41. Inter-Port Word-Line Short * Functional test complexity: O(N3) Cheng-Wen Wu, NTHU

  42. Inter-Port Bit-Line Short * Functional test complexity: O(N2) Cheng-Wen Wu, NTHU

  43. Address Scrambling Cheng-Wen Wu, NTHU

  44. 0/1 Reading Neighboring Cells • Read neighboring cells to detect inter-port faults: rN, rS, rE, and rW Cheng-Wen Wu, NTHU

  45. TAGS-PS Cheng-Wen Wu, NTHU

  46. Dual-Port RAM Test Cheng-Wen Wu, NTHU

  47. Compacted Dual-Port RAM Test * Time complexity: 10N Cheng-Wen Wu, NTHU

  48. Four-Port RAM Test * Time complexity: 17N Cheng-Wen Wu, NTHU

  49. Testing 6-Read-1-Write RAM * Time complexity: 13N Cheng-Wen Wu, NTHU

  50. Flash Memory Testing • Testing nonvolatile memories: • Masked ROM---exhaustive; pseudorandom • PROM (OTP) & EPROM---dummy row • EEPROM & flash memory---dummy row? • Testing flash memory core is hard • Customized core and I/O • Isolation (accessibility) • Reliability issues: disturbances, over program/erase, under program/erase, data retention, cell endurance, etc. • Long program/erase time Cheng-Wen Wu, NTHU

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