Hybrid Reachability Analysis for AMS Verification Using Support Functions and SMT Methods
This paper presents an innovative approach to reachability analysis for analog-mixed signal (AMS) verification. By integrating support function-based methodologies with SMT (Satisfiability Modulo Theory) techniques, we tackle the complexities introduced by digital effects in AMS systems. The study focuses on efficiently modeling digital and analog signals, accelerating reachability analysis, and adapting methods to handle nonlinear systems. Our experiments demonstrate significant improvements in the reachability process, including enhanced precision and speed, which are critical for verifying the performance of digitally-intensive Phase-Locked Loops (PLLs) and other AMS applications.
Hybrid Reachability Analysis for AMS Verification Using Support Functions and SMT Methods
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Presentation Transcript
Reachability Analysis for AMS Verification using Hybrid Support Function and SMT-based Method Honghuang Lin, Peng Li Dept. of ECE, Texas A&M University {linhh, pli} @neo.tamu.edu
Motivation Digital logic • Mixed-signal systems • Analog + Digital • Nonlinearity + Digital effects • Reachability Analysis • Formal method for AMS verification • Capable for PLL lock time checking TDC DCO Digitally-Intensive PLL [G. Yu et al JLPE’10]
Motivation • Challenges • Digital effects increase the complexity of the reachability analysis • Reachability analysis is expensive for nonlinear systems • Questions • Q1: How to model the two types of signals (especially digital) efficiently for verification? • Q2: How to accelerate reachability analysis?
Q1: Model • Linearization • TDC resolution effect • Complex transition • Digital Linear analog • Staircase Linear transition TDC
Q1: Model • Variable Reduction • IIR finite word length • Need state variables for internal nodes • Digital Linear analog • Reduce # state variables by 8 Multiplication: round-off error Addition: overflow Second order IIR
Q2: Reachability Analysis Acceleration • Support function based method • [A. Girard et al IFAC2008] • Initial space to reachable space • Support function representation • Efficient for linear systems • Unable to solve nonlinear systems Support function Reachable space
Q2: Reachability Analysis Acceleration • Simulation-assisted SMT based method • [L.Yinet al ICCAD2012] • Generic method for nonlinear systems • Discretize SimulationApproximationSATConservative • Suffers from resolution and dimension explosion • Our goal: accelerate this generic method by leveraging support function
Proposed Method AMS Pure analog model Reachability analysis • Digital Analog Support function based method Reachable space of the full system Linear subsystem Nonlinear subsystem SMT-based method
Outline • Motivation • Overview • Pure Analog Model with KRR • Hybrid Reachability Analysis • Experimental Results • Summary
Conservative Model Conservative? Upper bound Eu X Regression Eu Pure analog model Xa El Lower bound El Xd AMS System F Fa Fd Xa: Analog variables Xd: Digital variables Fa: Analog transition Fd: Digital transition X: Analog variables F: Pure analog transition function Eu: Upper bound of errors between F and Fa/d El: Lower bound of errors between F and Fa/d
Error Estimation with KRR • Kernel Ridge Regression (KRR) • [C. Saunders et al 1998; J.A.K. Suykenset al 2002] • Subject to • A.k.a Least Squares Support Vector Regression • Plenty of training dataaccurate prediction • Confidence interval computation • [K. De Brabanteret al 2011] • Error • Smootherbias and variance Min. structural risk
Error Estimation with KRR • Error Estimation of the Model • Next: Hybrid Reachability Analysis X(t) AMS system Ei(t+1) Error on the i-th state variable Pure analog model KRR Prediction + Confidence Intervals Features Targets
Partition the Pure Analog Model • Linear: • Nonlinear: • Variables on the boundary: Linearized
Hybrid Method Support function method NL-SMT with support function Combine the two reachable spaces with different dimension Reachable space with state variables , , Reachable space with state variables , ,
Support Function Based Method • Support function • Definition: • Intersection of half spaces: • Tight polyhedral over approximation of a reachable space • A list of vector li • Corresponding support function values ρ(li) • E.g. represent oval with pentagon
Support Function Based Method • Reachability analysis in linear subsystems • [A. Girard et al IFAC2008] • For the linear subsystem: • A useful property of support function: • The reachable space AU can be easily computed by the initial space U U AU A U AU AU+err Polyhedral over approximation
SMT Based Method • Nonlinear Satisfiability Modulo Theory(SMT) based method • [L.Yinet al ICCAD2012] • Convert verification problems to satisfiability problems composed of boolean combinations of multiple arithmetic constraints(can be nonlinear) • E.g. can be converted to • SAT solver • iSAT[http://isat.gforge.avacs.org/] • Davis-Putnam-Logemann-Loveland (DPLL) Algorithm • Produces an existing solution that satisfies all the constraints or “unsatisfiable”
NL-SMT with Support Function • Another Property of support functions: U V
Intersection of Reachable Subspaces • XY: Reachable space of linear subsystem • XZ: Nonlinear subsystem Linear Y Y Z X X Y Nonlinear Z X Z Y X Z X
Experiment Results • Error interval of modeling • KRR tool: Dlib-ml [Davis E. King, 2009] • Error intervals of phase difference and the output of loop filter for different word length • Reflects the error between digital implementation and ideal analog characteristic
Experiment Results • Speed up of the hybrid method • Compare single SAT solver running • Overhead in linear subsystem: 21.163 sec • At least 76X speedup
Hybrid Reachability Analysis of PLL • Lock time < 0.25 us • Resolution determined by the error interval prediction
Conclusions • Model with KRR • AMS Pure Analog • KRR • Hybrid Reachability Analysis • Model partition • Respective reachability analysis in the linear and nonlinear subsystems • Reachable subspaces intersections • Experiment Results • Model error • Speedup • DI-PLL lock time verification
Thanks • Questions?