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Agreements

Extended meeting (Nov.14,2005). Agreements. Sparsification in FADC should be demonstrated. If we are convinced of the sparsification performance, we take the FADC SVD_Finesse path as the main data stream. Multi-peak mode is prefered.

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Agreements

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  1. Extended meeting (Nov.14,2005) Agreements • Sparsification in FADC should be demonstrated. • If we are convinced of the sparsification performance, we take the FADCSVD_Finesse path as the main data stream. • Multi-peak mode is prefered. • Must be important for SuperKEKB, but do we really need it for SVD2.5 ? • Single-peak mode always available as a fallback option. Why not try multi-peak mode ! • List of data/control signals identified

  2. data control SVD2.5 readout L1/2 ladders APV25 L3/4 ladders VA1TA • Control signal paths should be determined • directly from FINESSE to repeater ? • sent from FINESSE through FADC to repeater ? • Timing information • Who produces what ? APV25 repeater VA1TA repeater new FADC (w/ sparsification) ADCTF PC farm SVD FINESSE TDM TTM Extended meeting (Nov.14,2005) TTD Event builder GDL L0T

  3. We choose to send control signals through the FADC system. Receive real timing signal digitization in our side if needed Extended meeting (Nov.14,2005) Issues to be discussed • During this week, we will try to agree on I/O between Finesse/FADC/Repeater. • Good trigger timing information is needed. • Digital or real timing ? • System works w/o CDAQ components. • Keep maximal freedom in our side

  4. Other things • Repeater • design: Cracow • production: Princeton (need confirmation) • tests: Vienna • APV25 procurement (1000pcs) • in progress by G. Hall (IC London) and D. Marlow (Princeton)

  5. data control Summary: SVD2.5 readout * L1/2 ladders APV25 L3/4 ladders VA1TA • Control signals sent from FINESSE through FADC to repeater. • Timing information • Receive real timing signal • digitization in our side if needed APV25 repeater VA1TA repeater ** new FADC (w/ sparsification) ADCTF PC farm * ** SVD FINESSE TDM TTM TTD Event builder GDL L0T

  6. To do • Start real design work • Resume DAQ meetings to avoid misunderstanding • Power lines • Schedule and documentation • More tests/studies • long cables b/w hybrids and repeater boards • study the sparsification algorithm

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