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This lecture provides an in-depth analysis of various Electronic Design Automation (EDA) tools utilized in the design, simulation, and synthesis of digital systems as part of the M.Tech Weekend Programme. Students will explore tools such as Viewlogic, Cadence Design System, ModelSim, and FPGA programming platforms like Xilinx and Altera. Additionally, the session covers hardware description languages (HDLs) including Verilog, ABEL, and AHPL, focusing on their applications in designing synchronous and asynchronous circuits. A comprehensive understanding of these tools and languages prepares students for advanced roles in electronic design.
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Lecture - 2 M.Tech. – Weekend Programme
EDA Tools1. Design Entry • View Logic • Mentor Graphics (Renoir) • Cadence Design System • OrCAD • ALDEC (Active HDL) • SimuCAD (Silos-3)
EDA Tools2.Design Simulation • Model Technology (Modelsim) • Synopsy • Cadence • SimulCAD (Silos-3) • Quick turn Design Systems (Power Suite) • View Logic (VHD Simulator)
EDA Tools3. Logic Synthesis 1. Synopsis • FPGA Expressway • FPGA Compiler 2. Synplify (Synplicity) 3. Exempler Logic (Leonardo Spectrum) 4. View Logic (Intelliflow) 5. Cadence Design System 6. Aldec (Active Synthesis)
EDA Tools4. Programmable Logic (Vendors) • Xilinx – Xilinx Foundation Series • Altera – MaxPlus II • Altera – Quartus II Ver. 4.0 • Lattice – isp Expert Compiler • Lucent – ORCA Foundary Development • Actel – FPGA Development System • Cypress- Warp2 • Atmel – FPGA Development System • Quick Logic – Quick works • Gate Field – ASIC Master
Other HDLs • ISPS (Instruction Set Processor Specification) • Behavioral Language • Used to design software based on specific hardware • Statement level timing control, but no gate level control
2. TI-HDL • TI-HDL (Texas Instruction Hardware Description Language) • Created a Texas Instruments • Hierarchical • Models Synchronous and asynchronous circuits • Non-extendable fixed data types
3. ZEUS ZEUS - Created at General Electric - Hierarchical - Functional Descriptions - Structural Descriptions - Clock Timing, but no gate delays - No asynchronous circuits
4. TEGAS • TEGAS (Test Generation And Simulation) • Structural with behavioral extension • Hierarchical • Allows detailed timing specification
5. Verilog • Verilog • Essentially identical in function in VHDL • Simpler and syntactically different • Gateway Design Automation Co. 1983 • Early de facto standard for ASIC programming • Open Verilog International Standard • Programming Language Interface to allow connection to non-Verilog code
6. ABEL • ABEL • Simplified HDL • PLD Language • Dataflow primitives e.g. registers • Can use to Program Xilinx FPGA
7. AHPL • AHPL (A Hardware Programming Language) • Dataflow language • Implicit Clock • Does not support asynchronous circuits • Fixed data types • Non-hierarchical
8. CONLAN • CONLAN (CONsensus LANguage) • Family of Language for describing various levels of abstraction • Concurrent • Hierarchical
9. ALTERA • ALTERA • Created by Altera Corporation • Simplified dialect of HDL • (AHDL: Altera HDL)
10. CDL • CDL (Computer Design Language) • Academic Language for teaching digital systems • Dataflow Language • Non-hierarchical • Contains conditional statements
11. IDL • IDL (Interactive Design Language) • Internal IBM Language • Originally for automatic generation of PLA Structures • Generalized to cover other circuits • Concurrent • Hierarchical
