1 / 68

ECE 471 / 571 – Energy-Efficient VLSI Design

ECE 471 / 571 – Energy-Efficient VLSI Design. Dr. Patrick Chiang TAs: Neil Glover; Li Hao Winter 2014 Tues/Thurs 12PM-2PM Slides: Courtesy Prof. Nikolic ( Berkeley), EECS 151, Spring 2006. Class Logistics. NOTE: Turn in Exam-2 and Final-Project together OH: TBD

sorley
Télécharger la présentation

ECE 471 / 571 – Energy-Efficient VLSI Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. ECE 471 / 571 – Energy-Efficient VLSI Design Dr. Patrick Chiang TAs: Neil Glover; Li Hao Winter 2014 Tues/Thurs 12PM-2PM Slides: Courtesy Prof. Nikolic (Berkeley),EECS 151, Spring 2006

  2. Class Logistics • NOTE: Turn in Exam-2 and Final-Project together • OH: TBD • Lab Hours: Fri., Li Hao, Neil Glover • Class is VERY lab intensive • HSPICE, unix, CAD • EXTRA GRADUATE STUDENT PROJECT • Come see me

  3. Two ‘Project’ paths • (1) Easy ‘Project’ course (recommended): • Advantages: • Easy project: sub-threshold 4b multiplier • Tool flow is easier (fictitious 0.25um process) • Cons: • Won’t be able to build a real chip at the end • May not understand the complexity of chip design • (2) Hard ‘Project’ course: • Only the MOST aggressive undergraduates should attempt; • Graduate students are REQUIRED for this. • 65nm-CMOS; • Advantages: • Real design block

  4. Three main issues in technology: POWER and ENERGY-EFFICIENCY VARIABILITY PERFORMANCE through PARALLELISM Big Picture

  5. Transistor count: (Wikipedia)

  6. Original Moore’s Law paper • ftp://download.intel.com/research/silicon/moorespaper.pdf • “Cramming more components onto integrated circuits” • “Heat problem: Will it be possible to remove the heat generated by tens of thousands of components in a single silicon chip?”

  7. Moore’s Law 670x complexity increase in ~ 10 years 2012 Intel-16nm 5M Gates/mm2

  8. More transistors than you have power Gap widening > 100x ‘DARK SILICON’ [2]

  9. Not enough power available Source: Bill Dally, 2011

  10. Need more off-chip bandwidth • nVidia Fermi (2010) Aggregate Microprocessor I/O Bandwidth* GDDR5: 200GB/s • IBM Power-7 (2009) DDR3: 100GB/s Local Links: ~20GB/s *F. O’Mahoney et al, “The Future of Electrical I/O for Microprocessors," VLSI-DAT, 2009.

  11. Cellphones bought in 2013 (growth in 2013) • Desktops/laptops bought 2013 (growth in 2013)

  12. QUESTIONS / BREAK

More Related