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Roadmaps, competitors

Roadmaps, competitors. MultiMarket Semiconductors BL Power Management 1 st Dec 2004. Roadmaps, competitors, Bosch feedback. BL Strategy MAPPS Silicon roadmaps, revisions Competitor benchmark tables Competitor technologies Bosch discussions on 300V switches. PM BL strategy.

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Roadmaps, competitors

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  1. Roadmaps, competitors MultiMarket Semiconductors BL Power Management 1st Dec 2004

  2. Roadmaps, competitors, Bosch feedback • BL Strategy • MAPPS • Silicon roadmaps, revisions • Competitor benchmark tables • Competitor technologies • Bosch discussions on 300V switches

  3. PM BL strategy • Reinforced in 2001 • PowerMOS up to 200V • Smart Power • Choices meeting Jan 2004 • Bidirectional switch mentioned • 600V FETS to be outsourced • Ongoing strategy process • Review in Sep 2004 • Not complete yet, but • More focus on auto markets? • Less reliance on VRM? • 600V – wait and see? • More focus on cost reduction?

  4. Silicon roadmap update – Nov 2004 • Silicon roadmaps now form part of the MAPPS structure • Performance and timings of silicon maps are largely unchanged, but • There are mismatches with some product roadmaps, hence • Actions needed to update the silicon roadmaps in next quarter are included • Some changes to likely technology solutions are included • Competitor benchmark tables are updated

  5. MAPPS • Initiative started 2003 • Aim for an integrated set of roadmaps, covering • Market • Applications • Product • Package • Silicon • 1st full set raised in Q2 2004 • Challenge for 2005 is to establish a process • Alignment & interaction • Plan to extend to equipment/process roadmaps

  6. Computing MAPPS set example • Add each map to presentation

  7. 2004 2005 2006 2007 2003 Si technology for DC:DC Motherboard: syncFETDriver = Integrated synchronous buck convertor Q2 2004 Key Parameters: 15/21.5 10/14 7/10 Rspec (mohm mm2) At Vgs = 10/4.5V Vds = 25V 12 10 9 2.5um pitch 0.5um trench 100nm TBO No DP 3.5um epi Red Phos Rds x Ciss mohm nF 2.0um pitch 200nm TBO DUV Graded epi

  8. 2004 2005 2006 2007 2003 Si technology for DC:DC Motherboard: syncFETDriver = Integrated synchronous buck convertor Q4 2004 Key Parameters: 15/21.5 10/14 7/10 Rspec (mohm mm2) At Vgs = 10/4.5V Vds = 25V 12 10 9 2.5um pitch 0.5um trench 100nm TBO 200nm TBO No DP optimise epi Red Phos Rds x Ciss mohm nF 2.0um pitch 1-1.5um pitch by self-aligned TR/CO DUV Actions: Revise/extend Rspec values, timings Add cost target Align with product map

  9. Competitor Benchmark Update (10th May 2004)VRM SyncFETn-channel LL silicon technology Ranked by Specific Rdson (10v)…. (estimated data shown green) Supplier Device Process V cell pitchcell specific Ciss * Qrr1 um shape Ron 10v Ron nC IR IRF7832 TR 30 1.8 stripe 15 8 5.9 Philips PH2625L TR 25 2.5 stripe 15 9 9.1 Infineon IPD04N03LA TR 24 2.2 stripe 16 8 10.9 NEC 2SK3405 TR 20 5.0off-sqr17 7 Renesas HAT2165H TR 30 2.2 stripe 17 104.6 Analogic AAT9125 TR 30 1.5 stripe 17 3.8 AO AO4430 TR 30 3.2 off-sqr 17 17 Rohm RQW250N03 TR 17 Siliconix Si4336DY TR 30 1.5 str + sqrs 18 127.2 Toshiba TPC8013H TR 30 3.3stripe 19 8 5.0 STM STS25NH3LL DMOS 30 2.2stripe 20 128.8 Philips PSMN005-30 TR 30 4.0 hex 21 16 13.2 Fairchild FDS7796 TR 30 2.5stripe22 11 8.0 Silic semi SSCS3001S DMOS 30 2.1 stripe 22 12 couldn’t meas

  10. Competitor Benchmark Update (10th November 2004)VRM SyncFETn-channel LL silicon technology Ranked by Specific Rdson (10v)…. (estimated data shown green) Supplier Device Process V cell pitchcell specific Ciss * Qrr1 um shape Ron 10v Ron nC Fairchild FDD044AN03L TR 30 1.4stripe13 9 9.7 Philips PH2625L TR 25 2.5 stripe 14 9 9.1 IR IRF7832 TR 30 1.8 stripe 15 8 5.9 Philips PH3330L TR 30 2.5 stripe 16 Infineon BSC022N03S TR 30 2.2 stripe 16 9 Siliconix Si4320DY TR 30 1.5 str + sqrs 16 1211.4 NEC 2SK3405 TR 20 5.0off-sqr17 7 Renesas HAT2165H TR 30 2.2 stripe 17 104.6 Analogic AAT9125 TR 30 1.5 stripe 17 3.8 AO AO4430 TR 30 3.2 off-sqr 17 17 Toshiba TPC8013H TR 30 3.3stripe 19 8 5.0 STM STS25NH3LL DMOS 30 2.2stripe 20 128.8 Philips PSMN005-30 TR 30 4.0 hex 21 16 13.2

  11. 2004 2005 2006 2007 2003 Si technology for DC:DC Motherboard: control FETDriver = Integrated synchronous buck convertor Q2 2004 Key Parameters: 15/21.5 11/15 9/12 Rspec (mohm mm2) At Vgs = 10/4.5V Vds = 25V 15 10 8 0.7 0.45 Rds x Qgd (mohm nC) 0.35 1.9 1.0 Rds x Esw (mohm mJ) 0.5 2.5um pitch 0.5um trench 100nm TBO No DP 3.5um epi Red Phos 200nm TBO Graded epi DUV (1+Rg).Rds.Es Gate silicide

  12. 2004 2005 2006 2007 2003 Si technology for DC:DC Motherboard: control FETDriver = Integrated synchronous buck convertor Q4 2004 Key Parameters: 15/21.5 11/15 9/12 Rspec (mohm mm2) At Vgs = 10/4.5V Vds = 25V 15 10 8 0.7 0.45 Rds x Qgd (mohm nC) 0.35 1.9 1.0 Rds x Esw (mohm mJ) 0.5 2.5um pitch 0.5um trench 100nm TBO Actions: Revise/extend Rspec values, timings Add cost target Align with product map 200nm TBO No DP optimise epi Red Phos (1+Rg).Rds.Es 2.0um pitch? DUV Gate silicide

  13. Competitor Benchmark Update (11th May 2004)VRM ControlFETn-channel LL/IL silicon technology Now ranked by (1+Rg) * switch energy 12v * Rdson FoM Supplier Device Process v cell cell specif Vgstx Qgd Rgate sw-en um geom Ron10v 250uA FoM ohm FoM Siliconix Si4390DY TR 30 4.2 stripe 27 1.7112 0.80.59 1.06 IR IRLR7821 TR 30 3.0 stripe 18 1.8314 1.3 0.47 1.08 Renesas HAT2168H TR 30 2.2 stripe 171.6023 0.4 0.79 1.12 STM STD38NH02L DMOS24 2.2stripe 20 1.58210.70.74 1.26 Infineon IPD06N03LA TR 25 2.2 stripe 161.7318 1.2 0.59 1.30 Toshiba TPC8013H TR 30 3.3 stripe 19 1.4818 1.9 0.56 1.62 Philips PH6325L TR 25 2.5 stripe 15 1.40151.90.70 2.03 NEC uPA2702GR TR 30 5.0 off-sqr 17 2.05232.01.01 3.03 SSC SSCS3002S DMOS30 2.1 stripe 22 (0.8)21 0.53 Fairchild FDS6294 TR 30 2.5 stripe 2722 ON NTD65N02R DMOS24 4.5 stripe 24 1.6830 1.11 Philips Gen 3.2 PA738 TR 25 4.0 stripe 23 1.40311.22

  14. Competitor Benchmark Update (10th November 2004)VRM ControlFETn-channel LL/IL silicon technology Now ranked by (1+Rg) * switch energy 12v * Rdson FoM Supplier Device Process v cell cell specif Vgstx Qgd Rgate sw-en um geom Ron10v 250uA FoM ohm FoM Siliconix Si4390DY TR 30 4.2 stripe 27 1.7112 0.80.59 1.06 IR IRLR7821 TR 30 3.0 stripe 18 1.8314 1.3 0.47 1.08 Renesas HAT2168H TR 30 2.2 stripe 171.6023 0.4 0.79 1.12 STM STD38NH02L DMOS24 2.2stripe 20 1.58210.70.74 1.26 Infineon IPD06N03LA TR 25 2.2 stripe 161.7318 1.2 0.59 1.30 Toshiba TPC8013H TR 30 3.3 stripe 19 1.4818 1.9 0.56 1.62 Philips PH6325L TR 25 2.5 stripe 14 1.40151.90.70 2.03 Philips PH8030L TR 30 2.5 stripe 16 1.40 1.9 NEC uPA2702GR TR 30 5.0 off-sqr 17 2.05232.01.01 3.03 Philips PHD96NQ03LT TR 25 4.0 stripe 23 1.40311.61.22 3.17 SSC SSCS3002S DMOS30 2.1 stripe 22 (0.8)21 0.53 Fairchild FDS6294 TR 30 2.5 stripe 2722 ON NTD65N02R DMOS24 4.5 stripe 24 1.6830 1.11

  15. VRM issues • Difficult balance of priorities • Rspec • Gate charge • Gate resistance • Die cost • Should VRM still be our main innovation driver? • If not, what should be instead? • Strategic direction requested

  16. Other roadmaps • Selected roadmaps to illustrate the main issues • Auto – add something that includes the 42V/300V mention - + product roadmaps, maybe package

  17. 2004 2005 2006 2007 2003 Si technology for AutomotivePower Train Q2 2004 Key Parameters: 40/88 27/~57 21/45 Rspec (mohm mm2) at 40/75V 175 200 2.5um pitch 0.5um trench Tj max (C) RSO Graded epi No DP thin epi Square cells New ET

  18. Competitor Benchmark Update 11th November 2004Automotive MosFET 40v n-chan SL D2pak etc Ranked by Specific Rdson (10v)…. (estimated data shown green) Supplier DeviceProcess cell cell typ specific Tjmax Rugg dataMeas example pitch shape BVd Ron 10v rating Eas EarSpEas Philips BUK7E2R2-40C TR 2.5 stripe 46 22 175 N.E.C. NP110N04PUG TR 2.0 stripe 25 175 Siliconix SUM110N04-03 TR 4.5 square 49 28 200 --- 0.21 0.069 I.R. IRF2804S TR 3.0 stripe 45 29 175 0.67 graph 0.077 Philips BUK763R1-40B TR 4.0 stripe 46 37 175 1.60 --- 0.093 STM STB200NF04 DMOS 7.0 stripe 45 51 175 1.20 --- 0.090 Infineon SPB160N04S2-03 DMOS 6.5 hex 49 52 175 0.81 0.03 N.E.C. NP88N04KUG TR 5.0 off-sqr 55 175 0.56 --- Philips BUK7604-40A TR 9.0 hex 46 57 175 1.60 --- Ruggedness data is spec minimum capability in J from data sheets (variety of conditions); SpEas (where shown) is Eas to destruction/AA in J/mm2 measured with L = 0.2mH

  19. 2004 2005 2006 2007 2003 Si technology for Automotivecost reduction for GPA Q2 2004 Key Parameters: 22.7 p Gen 3 25 mm2die cost (pence) 18.2 p 15.9 p 9 masks No DP stage No SN mask No AP mask No CB stage New ET for 55V tbf

  20. Competitor Benchmark – update 11th November 2004Smartpower HS switches Ranked by notional Die Cost (p) for a 20mO device – see notes for the derivation method. Only devices which have been obtained & analysed can be shown here. Mask count shown Green where estimated only * indicates double-layer metal logic interconnects used Supplier devicedesignMOSFET cell cell typ logic spec mask notional example date process pitch shape area Rdson count die cost um mm2 mO-mm2 20 mO100mO Infineon BTS5240G 2004 Trench 6.3 stripe 2.2 76 14 6.9 3.6 Philips BUK2138 2004 Trench 4 hex 4.4 47 15 8.3 6.2 IR IPS511S 1999DMOS16 hex 2.4 139 10 8.5 3.8 ST VN920SP 2001 DMOS 11 sqr 3.6 149 12 10.9 5.3 Infineon BTS740S2 1999 DMOS 12 sqr 3.7 162 11 11.0 5.2 Motorola MC33888 2001 DMOS 6 off-sqr 4.7 59 * 15 11.6 8.6 Philips BUK217 1998 Trench 11 hex 6.2 88 14 12.2 8.4

  21. Automotive issues • Still focused on 40V FETs • 75V FETs for 42V batteries now more doubtful • Is there a niche for RSO? • Application/market • Cost/performance • 300V more likely for electric hybrids • But timing unclear for volume market • Protected power trend away from monolithic……. • ….towards hybrid of Trench+ and control IC

  22. 2004 2005 2006 2007 2003 Si technology for mobile applicationsDriver = high side p-channel switch Q2 2004 Key Parameters: 47/70 Rspec (mohm mm2) Vgs = 4.5/2.5/1.8V Vds = 20V 47/70/105 35/53/80 2.5um pitch 0.5um trench Stripe cells 27/40/60 Moat Square cells (2um?) 18 (or 16nm) gate ox Low thermal budget Low substrate res DUV

  23. 2004 2005 2006 2007 2003 Si technology for mobile applicationsDriver = low side n-channel switch Q2 2004 Key Parameters: 15/22/33 11/17/25 Rspec (mohm mm2) Vgs = 4.5/2.5/1.8V Vds = 20V 8/12/18 2.5um pitch 0.5um trench No DP 3.5um epi Red Phos 2.0um pitch Square cells DUV

  24. Notes on mobile application roadmap Key Improvement Parameters • Rspec is typical chip Rds(on). Excludes package resistance (lead, wire, top metal). • Cost per function (Rspec) must show continuous improvement • Rspec capability at 1.8V (value ~ 50% higher than 2.5V) required Other desirable improvements • Option with ESD performance via poly diodes

  25. Notes on mobile application roadmap Parameters to maintain/relax existing performance • Vgs rating required is 12v for 20V Vds • Tj max 150C • No spec on ruggedness, gate resistance or switching loss • 2 layer metal option is not currently required Platform extensions • 30V, logic level Pchannel will be required for notebook load switch • 8V P channel and 12V N channel parts are offered by competitors, though no applications yet identified

  26. Notes for the Micro devices ranking tables SOT-23 = TO236AB SST3 Micro-3 SC96 M-pak TSOP-6 = SC74 SOT457 SMT6 SSOT6 Micro-6 SC95 SOT-6 TSMT6 VS6 SOT-363 = SC88 UMT6 SC70-6 Devices considered are 20v UL gate - Rdson shown is data sheet max value in mO at Vgs = 2.5v (per half for dual devices) * indicates device has gate diodes for ESD protection. Where two devices offered with/without ESD (same Rdson) the one with is shown as preference Suppliers considered for the ranking are the "normal group of 10" plus AO added by request of Roadmap meeting March 2004 Where a supplier is not shown, there are no relevant devices offered. Where there is a gap, no relevant devices in that package Overall ranking is based on the average of the separate rankings for the 3 packages The introduction date is shown, as from datasheet data etc The device cell structure and pitch in um shown. Where exact device has not been analysed, but estimated from others in near range, shown Green

  27. Competitor Benchmark – update (11th May 2004)Micro devices: n-channel 20v UL gateThe Rdson values shown are data-sheet max in mO for Vgs = 2.5v * indicates ESD gate protection

  28. Competitor Benchmark – update (10th November 2004)Micro devices: n-channel 20v UL gateThe Rdson values shown are data-sheet max in mO for Vgs = 2.5v * indicates ESD gate protection

  29. Competitor Benchmark – update (11th May 2004)Micro devices: p-channel 20v UL gateThe Rdson values shown are data-sheet max in mO for Vgs = 2.5v * indicates ESD gate protection

  30. Competitor Benchmark – update (11th November 2004)Micro devices: p-channel 20v UL gateThe Rdson values shown are data-sheet max in mO for Vgs = 2.5v * indicates ESD gate protection

  31. Competitor Benchmark Update (11 May 2004)LV p-channelThese are all 20v UL gate Trench devices Ranked by Specific Rdson (2.5v)…. (estimated data shown green) Supplier Device cell cell lowest specific Ciss * Vgs example pitch shape Vgs for Rds Ron 2.5v Rdson rating Siliconix Si4423DY 2.7 square 1.8 38 38 8 AO AO3411 3.2 off-sqr 1.8 39 50 8 ON NTHS4101PT12.4 1.8 40 53 8 Fairchild FDS4465 2.5stripe1.845 50 8 Analogic AAT8107 1.5 stripe 2.5 51 12 IR IRF7425 2.4 square 2.5 51 49 12 Infineon BSO201SP 2.2 stripe 2.5 56 55 12 NEC uPA1817GR 5.0 off-sqr 2.5 60 39 12 Toshiba TPCS8102 4.6 off-sqr 2.0 60 57 12 Fairchild FDS6575 4.0stripe 2.569 51 8 Philips (platform 4.4) 2.5 stripe 2.5 70 12

  32. Competitor Benchmark Update (11th November 2004)LV p-channelThese are all 20v UL gate Trench devices Ranked by Specific Rdson (2.5v)…. (estimated data shown green) Supplier Device cell cell lowest specific Ciss * Vgs example pitch shape Vgs for Rds Ron 2.5v Rdson rating Siliconix Si4423DY 2.7 square 1.8 38 38 8 AO AO3411 3.2 off-sqr 1.8 39 50 8 ON NTHS4101PT1 2.4off-sqr 1.844 548 Fairchild FDS4465 2.5stripe1.845 50 8 Analogic AAT8107 1.5 stripe 2.5 51 12 IR IRF7425 2.4 square 2.5 51 49 12 Infineon BSO201SP 2.2 stripe 2.5 56 55 12 NEC uPA1817GR 5.0 off-sqr 2.5 60 39 12 Toshiba TPCS8102 4.6 off-sqr 2.0 60 57 12 Philips PMV65XP 2.5 stripe 2.5 65 60 12 Fairchild FDS6575 4.0stripe 2.569 51 8

  33. 2004 2005 2006 2007 2003 Si technology for CCFL lighting Q2 2004 Key Parameters: 760 550 Rspec (mohm mm2) Vgs = 10V Vds = 200V 400 7um pitch 0.8um trench 2.5um pitch 0.5um trench No DP optimised epi Novel ET Deep trench resurf Square cells Graded epi

  34. 2004 2005 2006 2007 2003 Si technology for Notebook adaptors Q2 2004 Key Parameters: 168 130 100 Rspec (mohm mm2) Vgs = 10V Vds = 100V 4um pitch 0.8um trench No DP optimised epi Novel ET 2.5um pitch 0.5um trench RSO Graded epi

  35. Competitor Benchmark Update 11th May 2004100vMosFET n- channel SL gate D2pak etc Ranked by Specific Rdson (10v)…. (estimated data shown green) Supplier Device Process cell cell typical specific Ciss * meas pitch shape BVdss Ron 10v Rdson spEas Hitachi HAT2173H TR 2.2 stripe 108 51 Fairchild FDB3632 TR 3.0 stripe 115 38 IR IRFS4710 TR 2.4 stripe 112 144 67 Siliconix SUM110N10-09 TR 3.8 stripe 107 148 44 0.052 ST STB135N10 DMOS 155 39 Philips BUK7610-100B TR 4.0 stripe 120 164 39 0.050 NEC 2SK3479ZJ TR 5.0 off-sqr 170 86 Infineon SPB80N10 DMOS 8.0 hex 260 35 Mitsubishi FS70UM-2 TR 294 83 ON NTB52N10 DMOS 530 50 SpEas (where shown) is Eas to destruction/AA in J/mm2 measured with L = 0.2mH

  36. Competitor Benchmark Update 11th November 2004100vMosFET n- channel SL gate D2pak etc Ranked by Specific Rdson (10v)…. (estimated data shown green) Supplier Device Process cell cell typical specific Ciss * meas example pitch shape BVdss Ron 10v Rdson spEas Renesas HAT2173H TR 2.2 stripe 108 51 Fairchild FDB3632 TR 4.0 stripe 110 135 35 IR IRFS4710 TR 2.4 stripe 112 144 67 Siliconix SUM110N10-09 TR 3.8 stripe 107 148 44 0.052 ST STB135N10 DMOS 155 39 Philips BUK7610-100B TR 4.0 stripe 120 164 39 0.050 NEC 2SK3479ZJ TR 5.0 off-sqr 170 86 Infineon SPB80N10 DMOS 8.0 hex 260 35 Renesas FS70UM-2 TR 294 83 ON NTB52N10 DMOS 530 50 SpEas (where shown) is Eas to destruction/AA in J/mm2 measured with L = 0.2mH

  37. Competitor Benchmark Update 11th May 2004200vMosFET n- channel SL gate D2pak etc * indicates technology also available in SO-8 ($ Is SO-8, QLpak; but not D2pak) Ranked by Specific Rdson (10v)…. (estimated data shown green) Supplier Device Process cell cell typical specific Ciss Qgd pitch shape BVdss Ron 10v FoM FoM Siliconix SUM65N20-30 TR* 4.2 stripe 216 587 136 904 Fairchild FDB2670 TR* 6.0 stripe 230 710 141 1071 Philips PHK4NQ20T TR$ 7.0 stripe 220 755 128 905 Philips PSMN057-200B TR* 11.0 hex 235 790 148 1457 IR IRFB260N DMOS* 13.0 hex 222 890 130 2057 IR IRFB38N20D DMOS* 11.0 stripe 217 972 126 1204 Toshiba 2SK2401 DMOS 16.0 square 235 1200 247 1851 ON NTB30N20 DMOS 1340 157 1452 Renesas FS20UMA-4ATR 6.0stripe 1380 230 4143 Infineon BUZ30A DMOS 30.0 square 215 1490 125 3043 NEC 2SK3112 DMOS (N6-H) 1650 120 3000 ST STB19NB20 DMOS 22.0 stripe 229 2140 140 1817

  38. Competitor Benchmark Update 11th November 2004200vMosFET n- channel SL gate D2pak etc * indicates technology also available in SO-8 ($ Is SO-8, QLpak; but not D2pak) Ranked by Specific Rdson (10v)…. (estimated data shown green) Supplier Device Process cell cell typical specific Ciss Qgd pitch shape BVdss Ron 10v FoM FoM Siliconix SUM65N20-30 TR* 4.2 stripe 216 587 136 904 Fairchild FDB2670 TR* 6.0 stripe 230 710 141 1071 Philips PHK4NQ20T TR$ 7.0 stripe 220 755 128 905 Philips PSMN057-200B TR* 11.0 hex 235 790 148 1457 IR IRFB260N DMOS* 13.0 hex 222 890 130 2057 IR IRFB38N20D DMOS* 11.0 stripe 217 972 126 1204 ST STP40N20 DMOS 7.0 stripe 975 140 Toshiba 2SK2401 DMOS 16.0 square 235 1200 247 1851 ON NTB30N20 DMOS 1340 157 1452 Renesas FS20UMA-4ATR 6.0stripe 1380 230 4143 Infineon BUZ30A DMOS 30.0 square 215 1490 125 3043 NEC 2SK3112 DMOS (N6-H) 1650 120 3000

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