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Microelectronics User Group Meeting

Microelectronics User Group Meeting. Wrap-Up. TWEPP 2012, Oxford, UK 19/9/2012. Agenda. “News on foundry access services via CERN” by Kostas Kloukinas (CERN) (10’) “ 65nm technology: Design tools and foundry access services plans. ”

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Microelectronics User Group Meeting

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  1. Microelectronics User Group Meeting Wrap-Up TWEPP 2012, Oxford, UK 19/9/2012

  2. Agenda • “News on foundry access services via CERN” by Kostas Kloukinas (CERN) (10’) • “65nm technology: Design tools and foundry access services plans.” by Sandro Bonacini (CERN)(30’) • “Open Discussion with emphasis on 65nm technologies” (1h20’) Kostas.Kloukinas@cern.ch

  3. Overview of Technologies • Foundry services & Technology technical support provided by CERN. CMOS 8RF-LM Low cost technology for Large Digital designs CMOS 8RF-DM Low cost technology for Analog & RF designs BiCMOS 8WLCost effective technology for Low Power RF designs BiCMOS 8HP High Performance technology for demanding RF designs CMOS 6SF Legacy designs 130nm CMOS 250nm CMOS • Legacy technology IBM CMOS6SF (250nm) • Mainstream technology IBM CMOS8RF-DM (130nm) • Full support: CERN compiled Mixed-Signal design kit • BiCMOS variants are not very popular. • Advance technology IBM CMOS9LP/RF (90nm) • Limited support: Project specific. • Future technology (65nm) • For LHC upgrade applications. • Under evaluation. • No user support yet. CMOS 65nm High performance technology for dense designs CMOS 9SF LP/RF High performance technology for dense designs 65nm CMOS 90nm CMOS Kostas.Kloukinas@cern.ch

  4. 130nm MPW activity • CERN participates on all MOSIS MPW runs (4 runs/year)and organizes ad-hoc MPWs with the foundry for high volume and/or area demanding prototyping. • CMOS8RF-DM (3-2-3) is the dominant metal stack option. • Prototyping and Engineering run costs are kept the same for the last 2 years. • Evolution of the Prototyping activity on CMOS8RF for the last 5 years Kostas.Kloukinas@cern.ch

  5. Motivation for using a 65nm process • Future vertex detectors for high energy physics experiments can benefit from modern deep submicron technologies • Scaling is necessary to improve the performances of pixel detectors • Smaller pixel sizes (pitch) • More “intelligence” in each pixel • Faster serializers/deserializers • In general, the expected advantages in porting a front-end circuit to a more advanced technology include • A much more compact, faster digital part (reduction in area of ~60% compared to 130nm technology) • Better matching than in 130nm • Results of radiation hardness studies are very encouraging • See https://iopscience.iop.org/1748-0221/7/01/P01015/ , “Characterization of a commercial 65 nm CMOS technology for SLHC applications”, also presented in TWEPP 2011 • Radiation characterization of the selected technology is nevertheless needed • Foundry will be selected with a call for tender SandroBonacini - PH/ESE - sandro.bonacini@cern.ch

  6. Technology options & Metal stacks passivation • Plenty of device options… but they come at a cost! • Options modulate strongly the manufacturing cost. • Thin metals are expensive because of their fine pitch. • Must be taken into account at early design stages! RDL RDL M6 M6 • Wide choice of standard cell libraries from foundries • tapless/tap-cell (substrate/n-well contacts in each cell or not) • multi-Vt, multi-Vdd • power switches, isolation cells, level translators, … • several pitch sizes • 7-, 9-, 10-, 12-tracks, … • IP blocks from foundries • SRAMs, PLLs, SerDes, specialty I/O, … • … but radiation tolerance must be verified M5 M5 M5 mimcap M4 M4 M4 M3 M3 M3 M3 M2 M2 M2 M2 M1 M1 M1 M1 M1 M1 W W W W W poly poly STI SandroBonacini - PH/ESE - sandro.bonacini@cern.ch

  7. 65nm Technology Planning • To keep manufacturing cost at affordable levels and facilitate the exchange of IP blocks within the community it is proposed to support: • only one metal stack with a well defined set of technology options. • Low Power version of the process, with 6 +1 metal layers. • 4-thin, 1-thick, 1-UTM , RDL • Digital Standard cell Library: 9-tracks, standard-Vt • A second metal stack and library could be made available at a later. • CERN is seeking to establish a foundry access contract • Call for Tender is in process The procedure should complete before the end of 2012 • CERN plans to offer: • A Mixed Signal Design Kit that integrates the PDK and the Digital Standard Cell libraries and is compatible with the workflows of the 130nm Design Kit. • Provide access to foundry services via Silicon Broker. • MPWs, Engineering runs, Production runs. Kostas.Kloukinas@cern.ch

  8. 130 nm Mixed Signal Kit Distribution • Italy • INFN Rome • INFN Torino • INFN Bologna • INFN Bari • INFN Cagliari • Univ. of Bergamo • Univ. of Pisa • Univ. of Pavia • Polytecnico di Milano • US • Brookhaven Lab. • Columbia University • Fermilab • Lawrence Berkeley Lab. • Rutgers Univ. • Univ. of Chicago • Univ. of Hawaii • Univ. of Pennsylvania • Ohio State University • SMU,Dallas • Santa Cruz Institute • France • CEA SACLAY, Paris • IN2P3, Paris • LPNHE, Paris • IPNL, Lyon • IPHC, Strasbourg • LAPP, Annecy • LPC, Clermont-Ferrand • CPPM, Marceille • INPG, Grenoble • Germany • BergischeUniversität Wuppertal • DESY, Hamburg • Institut der Universitaet Heidelberg • Max-Plank-Institute fur Physik • Max-Plank-Institute Halbleiterlabor • ForschungszentrumJulich • University of Siegen • Universität Bonn • UK • Rutherford Appleton Lab. • Imperial College London • University College London CERN • Portugal • INESC, Porto • LIP, Lisbon • Switzerland • Universite de Geneve • Spain • Univ. of Barcelona • IFAE, Barcelona • IFIC, Valencia • Netherlands • NIKEF, Amsterdam • Poland • AGH Univ. of Science & Tech. Kostas.Kloukinas@cern.ch

  9. 65nm Design kit distribution & support Foundry • The role of the Silicon Broker will include • distribution of the package to HEP Institutes and give support • Maintenance of the PDK and libraries with updates from foundry • depending on frequency of updates and their complexity • Organization of workshop / training courses on the Mixed Signal flow • Reference design given as example • Organization of common MPW runs for users Silicon Broker Cadence VCAD design services CERN Physics institutes SandroBonacini - PH/ESE - sandro.bonacini@cern.ch

  10. 65nm Foundry Access Services CERN Physics institutes • Foundry Access • MPW as scheduledfrom Silicon Broker • Might have to adapt metal stack • Additional runs for HEP • Metal stack 4-thin, 1-thick, 1-UTM • Possibly every 4 months? • Engineering/production runs • Physics institutes can send the purchase order via CERN • GDS will be submitted directly to Broker Silicon Broker Foundry SandroBonacini - PH/ESE - sandro.bonacini@cern.ch

  11. Open discussion • 65nm Technology • Interest in the community • Designers have already started or will start very soon to explore a 65nm technology. • Organization of MPWs and Engineering runs • Standard cell libraries. • Repository of IP blocks. • 130nm technology • It is proposed that designers should sent to CERN a “bug list” and a “wish list” for the future releases of the CMOS8RF Mixed Signal Design kit. • Submission plans should be communicated to CERN early in advance. (Yearly submission planning). Kostas.Kloukinas@cern.ch

  12. Thank You Kostas.Kloukinas@cern.ch

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