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ADC Training

ADC Training. Peter Qian NSSH FAE. Agenda. Review of Definitions Sources of Distortion and Noise Common Design Mistakes ADCs from National Semiconductor. 111 110 101 100 011 010 001 000 1/8 1/4 3/8 1/2 5/8 3/4 7/8 FS

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ADC Training

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  1. ADC Training Peter Qian NSSH FAE

  2. Agenda • Review of Definitions • Sources of Distortion and Noise • Common Design Mistakes • ADCs from National Semiconductor

  3. 111 110 101 100 011 010 001 000 1/8 1/4 3/8 1/2 5/8 3/4 7/8 FS ANALOG INPUT (V) ACTUAL IDEAL Offset Error Offset Error NCG 9/99

  4. Full-Scale Error ACTUAL 111 110 101 100 011 010 001 000 1/8 1/4 3/8 1/2 5/8 3/4 7/8 FS ANALOG INPUT (V) IDEAL Full-Scale (Offset) Error NCG 9/99

  5. 111 110 101 100 011 010 001 000 1/8 1/4 3/8 1/2 5/8 3/4 7/8 FS ANALOG INPUT (V) Gain Error (Full-Scale Gain Error) Gain Error ACTUAL SHIFTED ACTUAL NCG 9/99

  6. SINAD = -20 * Log -SNR 10 -SNR 10 THD 10 THD 10 10 10 + 10 + 10 1 SINAD = 10 * Log 1 Signal-to-Noise and Distortion (SINAD)

  7. SINAD - 1.76 6.02 ENOB = 1 ENOB - Effective Number Of Bits • ENOB says that the ADC is equivalent to this (ENOB) number of bits as far as SINAD is concerned. That is, a converter with an ENOB of 7.0 has the same SINAD as a theoretically perfect 7-bit converter.

  8. Input Dynamic Range Dynamic Range is the ratio of the largest to the smallest possible signals that can be resolved. DO NOT confuse with Spurious Free Dynamic Range (SFDR). Resolution (Bits)Dynamic Range (dB) 6 36.0 8 48.1 10 60.2 12 72.2 14 84.3 16 96.3 18 108.4 20 120.4 Dynamic Range = 20 * Log(2n - 1) NCG 9/99

  9. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Signal 65dB SFDR Highest “Spur” SFDR - Spurious Free Dynamic Range

  10. Ideal Case • THD and SNR curves are linear • SINAD (and ENOB) maximum at –THD = SNR

  11. Actual Case • THD and SNR curves nonlinear near 0 dBFS input • SINAD (and ENOB) maximum a little below –THD = SNR

  12. Sources of Noise and Distortion

  13. Common Sources of Noise and Distortion • Inadequate Supply Bypassing • Inadequate VA - VDR* Supply Decoupling • Noisy Components/Conditioning Circuitry • Quantization • Clock • Output to Input Coupling * VDR (or DR VD) is the supply for the output drivers

  14. Noise Amplitude Jitter Excessive Clock Jitter (cont’d) Max Jitter = VIN / (2(n+1) VFS fIN)

  15. 3 Jitter Question Max Jitter = VIN / (2(n+1) VFS fIN) • How much jitter can be allowed in the following • 8 bit ADC • VREF = 2 Volts • ADC Gain = 1 • Maximum input of 1VP-P at 40 MHz ? Max Jitter = 2V / (2(8+1) 1V 40,000,000) Max Jitter = 2V / (512 40,000,000) Max Jitter = 31.1 ps

  16. Max Jitter = 1V / (2(8+1) 1V 40,000,000) Max Jitter = 1V / (512 40,000,000) 2 Jitter Question (2) Max Jitter = VIN / (2(n+1) VFS fIN) • How much jitter can be allowed in the following • 8 bit ADC • VREF = 1 Volts • ADC Gain = 1 • Maximum input of 1VP-P at 40 MHz ? Max Jitter = 15.5 ps

  17. Max Jitter = 2V / (2(12+1) 1V 40,000,000) Max Jitter = 2V / (8192 40,000,000) 3 Jitter Question (3) Max Jitter = VIN / (2(n+1) VFS fIN) • How much jitter can be allowed in the following • 12 bit ADC • VREF = 2 Volts • ADC Gain = 1 • Maximum input of 1VP-P at 40 MHz ? Max Jitter = 1.9 ps

  18. Max Jitter = 2V / (2(12+1) 1V 248,000,000) Max Jitter = 2V / (8192248,000,000) 2 Jitter Question (3) Max Jitter = VIN / (2(n+1) VFS fIN) • How much jitter can be allowed in the following • 12 bit ADC • VREF = 2 Volts • ADC Gain = 1 • Maximum input of 1VP-P at 248 MHz ? Max Jitter = 0.31 ps ! 3.1 ps Allowable Jitter with 0.1VP-P input?

  19. Signal Integrity Problem • Signals propagate down a line • Improper termination causes reflections • Reflections • Cause signal distortion • Cause signal radiation • Distortion • Leads to a change in timing • Can lead to timing uncertainty (jitter) • Jitter causes ADC output noise

  20. Reflection Problem • Signals propagate down a line • Improper termination causes reflections and signal distortion.

  21. tr 6 x tPR Length > - 4 When is Termination Needed? • Simple traces need not be terminated • Transmission Lines should be terminated • Trace becomes a transmission line at: Where tr is the digital signal rise time tPR is the signal propagation rate Typical tPR is about 150ps/inch on board of FR-4 material

  22. 440 A xpx f 140 A x f Length = > - Terminating Analog Lines • Analog signals are complex waveforms • For single frequencies, traces carrying analog signals become transmission lines at Where A is the zero-to-peak signal amplitude f is the signal frequency in MHz

  23. tr 6 x tPR 2 x 10-9 6 x 150 x 10-12 /in = > Length - 103 450 = 2.2 inches (5.6 cm) Maximum Length = 2 Question: Is Termination Needed? An ADC clock Signal has a 2ns rise time. The PCB is a typical one of FR-4 material. Beyond what line length should the line be properly terminated? ?

  24. Termination Techniques • Two Types of Termination • Series – Matches Driver Output to Line • Rsource + Rseries = ZO • A.C. – Matches Receiving end to Line • Series RC to Ground

  25. tr 6 x tPR > Length - 3 Series Termination • Series Termination: A Series Resistor • Source Impedance + Resistor = ZO • Resistor placed close to the source • Series Terminate When Source to Resistor Distance : tPR is approximately 150 ps/inch or about 59 ps/cm NOTE: See National Semiconductor’s Application Note AN-1113 (http://www.national.com/an/AN/AN-1113.pdf) for controlling line impedance.

  26. > L = Max Length - tr 6 x tPR 7 Series Termination Question 1 Develop a Rule of Thumb for the relationship between maximum line length and digital rise time before a trace must be treated as a transmission line ? L = tR / (6 x tPR ) L = tPR / (6 x 150ps/in) = tPR / 900 x 10-12 = tPR / 9 x 10-10 If tPR = 1 ns, then L = 1 x 10-9 / 9 x 10-10 = 10/9 inch per ns L = 1.1 inch per ns of rise time Or, for centimetersL = tPR / (6 x 59ps/cm) = tPR / 354 x 10-12 = tPR / 3.54 x 10-10 If tPR = 1 ns, then L = 10-9 / 3.54 x 10-10 =10/3.54 cm per ns L = 2.8 cm per ns of rise time

  27. > L = Max Length - tr 6 x tPR 7 Series Termination Question An ADC sometimes has bad data at the output. It is noted that the clock line is 6 inches long and the clock signal rise time is 2 ns. It is also noted that the ADC data output lines are 3 inches long and have 3.5 ns rise time. The data outputs go directly to an ASIC. What is the first thing you would do to try to solve this problem? ? Check to see if clock or data lines are long enoughto be considered transmission lines: L = 1.1 inch per ns of rise time tPR = 2ns, so max line length is 1.1 * 2 = 2.2 inches At 6 inches, the clock line should be treated as a transmission line. At 3.5 ns rise time, max length is 1.1 * 3.5 = 3.85 inches, So the 3 inch output data line length is o.k.

  28. 4 x tPR x L ZO C > - 2 A.C. Termination • A.C. Termination: Series RC to Ground at Destination. Needed for “Rat’s Nest” • R = ZO • C: Where L is the line length ZO is the characteristic impedance of the line tPR is the signal propagation rate down a board trace (about 150ps/inch with FR-4 board material)

  29. 4 x tPR x L ZO 4 x 150 x 10-12 x 7 50 C 84 pF > > > - - - 2 Question (A.C. Termination) A 7 inch long clock line with a 50-Ohm characteristic impedance needs a.c. termination on an FR-4 board. What is the value of the series resistor and the smallest capacitor that should be used? ? R = ZO = 50W

  30. ADC DesignConsiderations

  31. Agenda: ADC Design Considerations • The Analog Input • The Voltage Reference • The ADC Clock • The Digital Outputs

  32. The Analog Input

  33. 220 220 - + ADC Input Input 51 4.7k +5V 2K 430 pF -5V 3 Inadequate Conditioning Circuitry What is wrong with this circuit? 1) Gain of ~2 (could be unstable) 2) Possible problem driving sampling input

  34. 22 220 - + 47 ADC Input 220 22pF Input 62 47 430 +5V 2K 3.9 nF -5V 7 Better Conditioning Circuitry What is overall gain of this circuit? From Input Divider Amplifier Gain Circuit (47/(220+47)) * (220 / (22 * 430)/(22 + 430)) 0.176 * 11.51 = 2.026

  35. +VCM ADC12DL066 ADC12DL066 2V 0V IN+ IN- +0.5V -0.5V IN+ IN- +VCM VCM Single-Ended Input to Differential Input ADC NOT Preferred Way Best Way VCM can be any voltage from 1V to VA / 2. It is acceptable to use VRM. NOTE: Performance with a single-ended input signal is not as good as with a differential input signal !

  36. ADC121S625 IN+ IN- LMH6550 VCM Single-Ended Input to Differential Input Without a Transformer Best Solution for d.c. and low frequency applications

  37. ADC12DL066 2V 0V +1V –1V IN+ IN- VREF Differential Input 1.0 V Actual output Desired output 12 Single-Ended Customer Issue VREF = 1.0V. What value of (IN+) – (IN-) gives code of 000h? (IN+) – (IN-) = –1V (IN+) – (IN-) = 0 gives code of 800h or 1000 0000 0000 decimal (IN+) – (IN-) = +1V gives code of FFFh or 1111 1111 1111 decimal What are expected output codes? – peak = 0.0V + peak = 1.0V & output clipped > 1V Is the output as predicted? YES ! How should the input circuit look for correct conversion results? Min code: 800h Max code: FFFh What is the problem with this circuit?

  38. VCM ADC12DL066 IN+ IN- 2VP-P VCM 1 Recommended Single-Ended Circuit Here is a better way to bias the input circuit, ensuring that the input common mode voltage is at the mid-scale voltage of the input signal. NOTE: Performance with a single-ended input signal is not as good as with a differential input signal !

  39. ADC 2V 0V IN+ IN- VREF +1V 1.0 V 1 Recommended Single-Ended Input Circuit for D.C. Applications NOTE: Performance with a single-ended input signal is NOT as good as with a differential input signal !

  40. The Voltage Reference

  41. Ramp with Quiet Reference

  42. Ramp with Noisy Reference

  43. 1 Why Noisy Reference is Worse at High Input Voltages From ABCs of ADCs : Output = 2n x G x AIN / VREF So, as the input increases so does the output code and an error in AIN is a larger error when AIN is larger.

  44. Clean Reference and a Sine Wave

  45. Noisy Reference Effect Upon a Sine Wave

  46. Clean Reference and a Sine Wave – FFT Note SNR & Noise Floor

  47. Noisy Reference Effect Upon a Sine Wave – FFT Note SNR & Noise Floor

  48. 5K 15K +3V 0.1 +3V +3V 316 + - 0.1 1K 2N3906 +3V + - 5.49K REFT 10K 0.1 178 10K 11K CM 1.5K +3V 0.1 178 +3V + - 0.1 REFB - + 1K 0.1 10/10V 10K 2N3904 10/10V 0.1 316 5 How NOT to Build a Reference What is wrong with this circuit? Too Many Components Collector in Feedback Path Too Many Amplifiers Too many different resistor values

  49. 10K EXTT +5V +5V 10uF, 6V 0.1 +5V 0.1 - + 82 750 100 2N3904 2K 4.7K LM4040-4.1 1.5K 750 2K +5V 0.1 1.5K + - 470 100 2N3906 10 uF, 6V 100 0.1 -V -V 10K EXTB 13 A Better Reference Circuit What is the nominal range of voltages for EXTT and EXTB? EXTT min = 4.1 * 0.75/(0.75+2+0.75) = 0.88V EXTT max = 4.1 * (0.75+2)/(0.75+2+0.75) = 3.22V EXTB min = 4.1 * (0.47)/(4.7+2+0.47) = 0.27V EXTB max = 4.1 * (0.47+2)/(4.7+2+0.47) = 1.41V

  50. Keep Reference Quiet! • Use a Tight Layout • “Star” Ground for all Components and Reference Grounds of ADC • Ground Via Enters Ground at Quiet Point

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