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EECS 170C Lecture Week 1

EECS 170C Lecture Week 1. Lowpass Filter Example. ideal op-amp. From standard circuit analysis:. Specifications:. ideal op-amp. Lowpass Filter Design. 2 equations with 3 unknowns  not a unique solution!. Additional constraint #1:. Capacitors should be no larger than 1 pF:.

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EECS 170C Lecture Week 1

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  1. EECS 170C LectureWeek 1 Prof. M. Green / U.C. Irvine

  2. Lowpass Filter Example ideal op-amp From standard circuit analysis: Prof. M. Green / U.C. Irvine

  3. Specifications: ideal op-amp Lowpass Filter Design 2 equations with 3 unknowns  not a unique solution! Prof. M. Green / U.C. Irvine

  4. Additional constraint #1: Capacitors should be no larger than 1 pF: Set C2 = 1 pF R2 = 318  R1 = 159  Additional constraint #2: For f > f3dB, magnitude should exhibit -40 dB/decade rolloff: -20 dB/decade The given circuit topology cannot satisfy this constraint. f3dB f Prof. M. Green / U.C. Irvine

  5. 2nd-order filter topology (2 capacitors) needed: Additional constraint #3: Under the condition that R’s and C’s vary randomly within ±10%, f3B should vary no more than ±5% This constraint is impossible to meet for any RC filter! Prof. M. Green / U.C. Irvine

  6. VG Vin Vout Vin Vout Possible solution #1: Replace resistors with triode-biased MOSFETs with gates controlled by dc voltage VG, realizing electrically controllable resistors. Critical frequencies can be controlled by VG. Possible solution #2: Replace resistors with configuration consisting of capacitor and switches, with switches controlled by clock signal with period Tc. Critical frequencies are determined by Tc and capacitor ratios. Critical frequencies can be controlled by Tc. Prof. M. Green / U.C. Irvine

  7. Aspects of Design (Synthesis) • Desired behavior & specifications are given; component values & circuit topology are not. • Solution is usually found iteratively: An initial circuit is proposed and analyzed. If specifications are not met, the circuit is modified and re-analyzed. • There is usually not a unique solution that satisfies the specifications. However, each solution exhibits its own set of tradeoffs (e.g., size, cost, robustness) that must be considered. • It may not be possible to meet all of the specifications simultaneously using a given technique or technology. Prof. M. Green / U.C. Irvine

  8. Analog vs. Digital Signal Representation Precision in specifying and measuring voltage signal is determined by random noise generated by circuit components. Dynamic Range is determined by ratio of maximum amplitude (usually determined by supply voltage) and noise level. Analog representation: Dynamic Range in specifying and measuring digital signal is determined by number of bits used in representing the signal. Digital representation: 16 possible digits  Dynamic Range = 16 Prof. M. Green / U.C. Irvine

  9. Continuous vs. Discrete Methods of Timing Voltage signal is defined at any arbitrary instant of time. There is no limit on the highest frequency that can be generated or measured. Continuous-time signaling: Voltage signal is defined only at discrete values of time kT, where k is an integer. The highest frequency that can be observed is 1/2T – the Nyquist frequency. Discrete-time signaling: Prof. M. Green / U.C. Irvine

  10. Passive Components Power dissipation in a resistor: Components that always dissipate power are said to be passive. Power supplied by VS: Power dissipated in RL: Power gain: Power amplification is impossible if only passive components are present. Prof. M. Green / U.C. Irvine

  11. Active Components A component that is not passive is said to be active. (assuming rin >> RS , rout << RL) Power amplification is possible with active devices -- that’s why we need transistors. Prof. M. Green / U.C. Irvine

  12. Discrete Circuit Realized on a Printed Circuit Board (PCB) Prof. M. Green / U.C. Irvine

  13. Integrated Circuit on a Monolithic Substrate Prof. M. Green / U.C. Irvine

  14. Circuit Realization:Discrete vs. Monolithic • Each component takes roughly the same area on the board independent of its value. • Passive components can be chosen to a desired accuracy, subject to cost. • Most circuit nodes can be observed for testing and verification. • Dimensions on order of cm. • The area of a component is directly related to its value. • Individual component values exhibit large variances; however, like components with identical geometries in close proximity exhibit very close matching (<1%). • Access to the circuit is only through pre-determined nodes that are connected to pads which then bonded out to the package. • Dimensions on order of mm, encapsulated in a package. Prof. M. Green / U.C. Irvine

  15. Example of Matching Design an amplifier with an accurate gain of +10: Assume Av can take values between 10,000 and 50,000. Very small depends only on resistor ratio Let R1 = 9k , R2 = 1k: Av = 10,000  Vout /Vin = 9.990 independent of individual resistor values Av = 50,000  Vout /Vin = 9.998 Prof. M. Green / U.C. Irvine

  16. X X X Manufacturability of ICs 1. Die Size Prof. M. Green / U.C. Irvine

  17. 2. Power Dissipation Power dissipated in the IC is converted to heat, raising the temperature of the die & package. Elevated die temperature can degrade circuit performance or even permanently damage the silicon. To accelerate heat removal, a heat sink may need to be used, requiring more space. Passive heat sinks Active air-cooling heat sink Prof. M. Green / U.C. Irvine

  18. 3. Robust Design • IC must operate properly in the presence of variations in: • Processing in fabrication technology • Individual component values can vary ±15% or more • Voltagesupply • Supply voltages can vary ±10% • Temperature • Circuit should operate to spec at 0--70° C ambient temperature “PVT” Prof. M. Green / U.C. Irvine

  19. Use of Approximation KCL at Vout: KCL at VX: Prof. M. Green Univ. of California, Irvine Prof. M. Green / U.C. Irvine 19

  20. My Research 1. High-speed frequency divider: The operation of “real” high-speed clock dividers is more complex … Prof. M. Green / U.C. Irvine

  21. Clock divider based on CML D flip-flop: Divider sensitivity curve: Vmin = minimum input clock amplitude required for correct operation. (function of input frequency) fso = self-oscillation frequency Vmax = maximum dc differential voltage that can be applied to the input clock for which the circuit self-oscillates. Vmax Prof. M. Green / U.C. Irvine

  22. Divider test chip measurements Divider chip photograph Measured sensitivity curves: Conventional (DFF) divider Modified regenerative divider Ring oscillator divider Designed at Broadcom using 0.13 µm CMOS process; shunt-peaking was used. Prof. M. Green / U.C. Irvine

  23. 2. Equalization of broadband receivers: • Normally the equalizer and CDR are designed and implemented as separate blocks. • Common elements in each of the two blocks can be identified and combined... Prof. M. Green / U.C. Irvine

  24. Circuit Details • Shunt-peaking CML summer. • 2-stage shunt-peaking CML slicer. • Differentially-tuned LC VCO. • Retimer generates low-ISI retimed data. Prof. M. Green / U.C. Irvine

  25. Measurement Setup Die photo. Implemented in Jazz Semiconductor 0.18µm BiCMOS Process (only CMOS transistors used). Test setup Test board Prof. M. Green / U.C. Irvine

  26. Equalizer + CDR Operation (2) 2.4 m cable Cable output eye diagram. Recovered clock RJ = 1.83 ps rms Retimer output eye diagram Jitter = 4.14 ps rms 3.6 m cable Cable output eye diagram. Recovered clock RJ = 2.15 ps rms Retimer output eye diagram Jitter = 4.96 ps rms Prof. M. Green / U.C. Irvine

  27. ÷2 ÷2 PLL 2. Equalization of broadband receivers: 4:1 Multiplexer Tree Structure: Din0 Q D D-FF A Din1 B Select Q D D Q D Q A Dout retimer Latch D-FF D-FF B Select 10 GHz Din2 D Q D Q 40 GHz 20 GHz Q D Latch D-FF D-FF A B Select Din3 Q D Q D 20 GHz Latch D-FF 10 GHz 20 GHz 40 GHz 10 GHz 10 GHz Prof. M. Green / U.C. Irvine

  28. 40GHz Differential Push-PushVCO Resonates at 40 GHz Virtual ground node Resonates at 20 GHz Prof. M. Green / U.C. Irvine

  29. Chip Board and Die Micrograph 40 Gb/s output 20 GHz clock 40 Gb/s output 20 GHz clock output 40Gb/s Distributed buffer Push-push differential VCO 625 MHz Reference clock PLL Clock buffers 40Gb/s MUX and retimer 20Gb/s inputs 20 Gb/s inputs Prof. M. Green / U.C. Irvine

  30. Measured 40 Gb/s Output 40Gb/s MUX output (Differential) with 450 mV differential peak-to-peak vertical eye opening and 1.14 ps rms jitter Prof. M. Green / U.C. Irvine

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