Post-Routing BEOL Layout Optimization for Improved TDDB Reliability

1. Post-Routing BEOL Layout Optimization for Improved Time-Dependent Dielectric Breakdown (TDDB) Reliability Tuck-Boon Chan and Andrew B. Kahng VLSI CAD LABORATORY, UC San Diego

2. Outline • TDDB Reliability • Our work: reducing TDDB Margin • Signal-aware TDDB Analysis • Post-routing Layout Optimization • Experimental Results and Conclusions

3. Motivation • Time-dependent dielectric breakdown (TDDB) • A dielectric forms a conductive path between the interconnects due to electrical stress  chip functional error! • Breakdown time, tfαexp (-γEm) [Zhao11] • Electric field (E) across dielectric is increasing [ITRS2011] E increases linearly  tf reduces, TDDB risk TDDB reliability limits (1) wire density and/or (2) max. voltage

4. Via-to-Wire Spacing is Critical • Dielectric btw. via and wire is most susceptible to TDDB • Small spacing is further reduced by mask misalignment between via and wire • Smaller spacing  higher electric field  shorter lifetime

5. Our Work (1) • A chip-level TDDB reliability model • Enable signal-aware TDDB analysis

6. TDDB Model • Dielectric breakdown time is modeled as a Weibull distribution [Bashir10] Weibull shape factor Failure probability Fij(t) = 1 – ( exp(-t/nij)β ) Characteristic lifetime nij = A exp(-γ(V/Sij)m ) Supply voltage Spacing

7. Chip Level TDDB Reliability • Apply Poisson area-scaling law to estimate chip failure rate Fchip(t) = 1 – ( exp(-t  H-1G)β ) [Bashir10] G = Σij[ exp(-t γ(V/Sij)m) (Lij)1/β ] αij Sij wirej Stress factor: probability of interconnects being stressed viai Lij

8. Signal-Aware Analysis • Typical TDDB analysis assumes interconnects are under “DC stress”  too pessimistic! • Obtain stress factors by running cycle-accurate logic simulation  too slow • Proposed method: Use state probability from vector-less logic simulation  much faster P1i + P1j if (1-P1i) > P1j { αij (1-P1i) + (1-P1j) otherwise Worst-case stress ratio for a pair of state probabilities 0 1 net i net j 0 1 time stressed stressed

9. Our Work (2) • Post-route layout optimization • Shift wire edges around vias to increase via-to-wire spacing • Negligible effect on circuit timing  Does not require additional design iterations Applicable at post-route or mask writing

10. Post-Routing Layout Optimization Design Netlists Original Layout Inputs TDDB analysis and layout optimization flow Alternative layout implementation State probability Calculate TDDB reliability Original layout + Marker layers Signal-aware analysis (optional) Layout optimization Modified layout

11. Defining Segments for Perturbation via Define movable edges for layout optimization wire Shift this edge to increase spacing TDDB critical region Shift this edge to preserve wire width Overlappedregion

12. Shifting Wire Edges • Shift wire edge to increase via-to-wire spacing • Shifting is not applied if it violates via enclosure rule

13. Experiment Setup • 4 Benchmark circuits • Synopsys 32nm library • 160nm metal pitch • Analyze TDDB on M2, M3 & M4

14. Layout Optimization Results • Layout optimization  ~110% lifetime • Signal-aware analysis  ~200% lifetime

15. Timing Impact of Layout Optimization • 40% of nets are modified • ΔR per net < 0.3 Ω, ΔC per net < 0.1 fF, • Average gate-worst Δdelay = 0.012ps, • Add total ΔC at driver’s output pin • Average wire-worst Δdelay = 0.012ps • Add total ΔC at receivers’ input pin • Add total ΔR at driver’s output pin

16. Conclusions • TDDB is a reliability issue for BEOL • Limits pitch scaling and/or supply voltage • Signal-aware TDDB analysis  2X chip lifetime • Post-routing layout optimization  +10% chip lifetime with negligible impact on timing

17. Thank you!

18. References • [Achanta06] R. S. Achanta, J. L. Plawsky and W. N. Gill, "A Time Dependent Dielectric Breakdown Model for Field Accelerated Low-k Breakdown Due To Copper Ions”, AIP Applied Physics Letters 91 (23) 2006, pp. 234106-1 - 234106-3. • [Bashir10] M. Bashir and L. Milor, “Towards a Chip Level Reliability Simulator for Copper/Low-k Backend Processes”, IEEE Design Automation and Test in Europe, 2010, pp. 279-282. • [Berman81] A. Berman, “Time-Zero Dielectric Reliability Test By a Ramp Method”, IEEE Intl. Reliability Physics Symposium, 1981, p. 204. • [Chen06] F. Chen, O. Bravo, K. Chanda, P. McLaughlin, T. Sullivam, J. Goill, J. Lloyd, F. Kontra and J. Aitken, “Comprehensive Study of Low-k SiCOH TDDB Phenomena and Its Reliability Lifetime Model Development”, IEEE Intl. Reliability Physics Symposium, 2006, p. 46. • [Lee88] J. Lee, I. C. Chen, and C. Hu, “Modeling and Characterization of Gate Oxide Reliability”, IEEE Intl. Reliability Physics Symposium, 1988, p. 2268-2278. • [Lloyd05]J. R. Lloyd, E. Liniger, and T. M. Shaw, “Simple model for time-dependent dielectric breakdown in inter- and intralevellow-k dielectrics”, AIP Journal of Applied Physics98, (084109) (2005), 084109-1 – 084109-6. • [Zhao11] L. Zhao, Z. Tőkei, K. Croes, C. J. Wilson, M. Baklanov, G. P. Beyer, and C. Claeys, “Direct Observation of the 1/E Dependence of Time-Dependent Dielectric Breakdown in the Presence of Copper”, AIP Applied Physics Letters 98 (03) (2011), pp. 032107-1 - 032107-3.