1 / 15

Development and Design Overview of BOLC/BOLA Instrumentation System

The BOLC/BOLA instrumentation system is designed to support advanced measurements with multiple electrical components. The setup includes four types of electrical boards handling various functionalities, including analog and digital signal processing. The mechanical aspects involve a robust enclosure for board stacking and thermal management. Ongoing development stages include testing of hardware prototypes and validation of electronic designs. Comprehensive documentation outlines power consumption, mass specifications, and quality assurance activities to ensure operational reliability.

teague
Télécharger la présentation

Development and Design Overview of BOLC/BOLA Instrumentation System

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. BOLC / BOLASAp/DAPNIA/DSM/CEAC. CARAWE Design Team:A. BOUERE - N. DEVIN - G. DHENAIN - E. DOUMAYROU M. SEYRANIAN - D. SCHMITT - T. TOURRETTEQA/PA:N. COLOMBEL - L. DUMAYE - F. LOUBERE - V. MAUGUENAIV:C. BONNIN - …Test Equipments:F. DALY - P. DE ANTONI - M. DONATI - E. POINDRON BOLC/BOLA

  2. BOLC/BOLA Design (1) • BOLC design • Electrical • 4 board types: • BAB (Bolometer Analog Board) - 5 x 32 analog channels • BIAS (Bolometer Bias & Clock translator) - x 3 • DAQ_IF (Data Acquisition & transfer to DMC) - 1 M + 1 R • BOLC_BP (passive BackPlane) - x1 • 1 independent module: • PSU (Power Supply) • Mechanical • Electronics boards are mounted on stiffeners • Modules (electronics boards+stiffeners) - x10 - are plugged and locked into an enclosure which also supports the backplane • PSU BOLC box bottom (mechanical & thermal IF specified) BOLC/BOLA

  3. BOLC/BOLA Design (2) Connectors to/from FPU (x18) Top cover Connectors to/from DMC (x4) BOLC main box Primary Power + bonding stub Secondary power Connectors PSU BOLC/BOLA

  4. BOLC/BOLA Design (3) • BOLA design • Electrical • 2 board types: • B_BOLA (Diff Amp.*+Filter for Blue Bolometer): x4 • R_BOLA (Diff Amp.*+Filter for Blue Bolometer): x2 * Diff Amp. Uses JFET pairs (x160) • Mechanical • Electronics Boards are mounted on individual stiffeners • Modules (Board+stiffeners) are stacked • Top cover & base plate (with feet) on each side of the « stack » BOLC/BOLA

  5. BOLC/BOLA Design (3) Top cover “BLUE” Modules (x4) “RED” Modules (x2) Base plate with feet BOLC/BOLA

  6. BOLC/BOLA Status (1) • Status: • H/W • Readout: • 8 channel prototype (BAB) functionally tested - Awaiting for performance tests on real bolometers • BIAS board designed (waiting for spec. Validation) • BIAS FPGA is ready • SimBOLC BIAS fabrication started (avail. 4/03) • BOLA modelling in progress • New grounding scheme under preparation * • Control: • DAQ_IF FPGA VHDL ready - • SIMBOLC DAQ_IF under fabrication (avail. 04/03) • 300mK temperature channel design is validated (jan. 02) • « >1K », Heater control design tests in progress ( end of march) • Mechanical • Overall Design (Stiffener+box) are ready • Detailed Design is started (13/02) * (elec.+meca. grounds inside BOLC) BOLC/BOLA

  7. BOLC/BOLA Status (2) • Status …: • Test Equipments • LTU • Preliminary specification available • Full specification in progress • Software specification is started • FPU simulator • Specification available • Electronics Boards in fabrication • Software implementation in progress • BOLG (BOLA test cryostat) • “Pulse tube” cooler available • Cryostat specified • Documentation • BOLC/BOLA Specifications - SAp-PACS-CCa-0024 - 1.0 • BOLC/BOLA ICD - SAp-PACS-CCa-0024-00 - 1.0 • BOLC/DMC E ICD - SAp-PACS-CCa-0046-01 - 1.1 • FPU simulation Specifications -SIG-PACS-PDA-0013-01 - 1.0 • Instrument Description Document contribution: BOLC/BOLA units description BOLC/BOLA

  8. BOLC Outer envelope: 382,5 x 289 x 333,5 (L x D x H - mm) Mass 18.25 kg (previous) 15.25 kg (updated) Allocation *: 14.5 kg Power consumption Max. Average: 44.22 W Allocation: 35 W * Refer to IID-B 2.0 Budgets BOLA • Outer envelope • 162 x 119 x 121 (L x D x H - mm) • Mass • 1.7 kg Allocation: 2.6 kg • Power dissipation • Average: 0.2 W Allocation: 0.2 W BOLC/BOLA

  9. Models Definition • From “Development Plan” document: • BreadBoards: to validate electronics designs (in particular: detector readout & drive electronics) * • STMs: to validate (vibration & thermal) BOLC, BOLA, PSU mechanical structure * • Simulator: to validate IF with DMC - BOLC only * • EMs: to perform electrical compatibility tests PSU-BOLC - PSU only* • QMs: • QM1: to validate design & electrical IF with PhFPU • QM2: full qualification model * • FM: full model … • FS: spare boards only * : not for delivery BOLC/BOLA

  10. Models Summary BOLC/BOLA

  11. PA / QA Plan & Activities • Documentation available: • Standard Product Assurance Plan: • SAp-GERES-FLo-436-00 issue 1.0 of 09/11/2000 • BOLC/BOLA DCL: • SAp-PACS-VM-0058-01 issue 10 of 01/2002 • BOLC/BOLA DML: • SAp-PACS-NC-0071-02 issue 0 of 01/2002 • BOLC/BOLA DPL: • SAp-PACS-NC-0072-02 issue 0 of 01/2002 • Documentation in preparation: • BOLC/BOLA FMECA • Draft available • Final document in correction/amendment phase: • Available by end of February (ref: SAp-FLo-0082-02) BOLC/BOLA

  12. AIV Plan & Activities • AIV activities diagram is available for • QM1 • QM2 • FM • Test configurations document is available in draft form • Test equipments required are identified & defined • Factory Support Equipment (FSE) for post-fabrication testing (1 per electronics board) • Local Test Unit (LTU) for DMC interface simulation • FPU simulator for PhFPU simulation BOLC/BOLA

  13. Problem Areas (1) • BOLA thermal interface with S/C • Problem: minimum operating temperature (120K) not accepted by ESA. • Solution(s): • Evaluate performance (mainly noise) of JFET at lower temperature (≥ 50 K) • Built up of BOLA thermal model (JFET self heating evaluation) • BOLC mechanical interface with S/C • Problem: Need for formal agreement to proceed with mechanical manufacturing • Solution(s): depends on boxes configuration on panel • H/W is frozen: mechanical design update is difficult • Connector back-shell update BOLC/BOLA

  14. Problem Areas (2) • BOLC specification confirmation: • Problem: still waiting for detector test results • Solution(s): start designing boards not dependent of bolometer characteristics (DAQ_IF & BackPlane) • Component cost • Problem: current estimation exceed initial estimation • Solution(s): • … BOLC/BOLA

  15. Schedule / Milestones BOLC/BOLA

More Related