Matteo Porro on behalf of the DSSC Consortium

1. The DSSC project for XFEL: DEPFET and readout ASIC8th International Meeting on Front End ElectronicsBergamo, 26.05.2011 MatteoPorro on behalf of the DSSC Consortium

2. DSSC Consortium • M. Porro1,2, L. Strueder1,2, G. De Vita1,2, S. Herrmann1,2, D. Muentefering1,2, G. Weidenspointner1,2, L. Andricek2,3, A. Wassatsch2,3, P. Lechner8, G. Lutz8, C. Sandow8, S. Aschauer8, P. Fischer6, F. Erdinger6, A. Kugel6, T. Gerlach6, K. Hansen7, C. Reckleben7, I. Diehl7, P. Kalavakuru7, H. Graafsma7, C. Wunderer7, H. Hirsemann7, C. Fiorini4,5, L. Bombelli4,5, S. Facchinetti4,5, A. Castoldi4,5, C. Guazzoni4,5, D. Mezza4,5, V. Re10, M. Manghisoni10, U. Pietsch9, T. Sant9 • 1) Max Planck InstitutfuerExtraterrestrischePhysik, Garching, Germany • 2) MPI Halbleiterlabor, Muenchen, Germany • 3) Max Planck InstitutfuerPhysik, Muenchen, Germany • 4) DipartimentodiElettronica e Informazione, Politecnicodi Milano, Milano, Italy • 5) Sezionedi Milano, Italian National Institute of Nuclear Physics (INFN), Milano, Italy • 6) ZentralesInstitutfürTechnischeInformatik, Universitaet Heidelberg, Heidelberg, Germany • 7) DeutschesElektronen-Synchrotron DESY, Hamburg, Germany • 8) PNSensorGmbH, Muenchen, Germany • 9) FachbereichPhysik, Universitaet Siegen, Siegen, Germany • 10) Dipartimentodiingegneriaindustriale, Universitàdi Bergamo, Bergamo, Italy

3. Outline • Detector Requirements • Detector System Overview • Non-Linear DEPFET Detector working principle • Detector expected performance: • Speed • High Dynamic Range • Single Photon Resolution • ASIC architecture • First experimental results • Conclusions

4. Bunch structure of the European XFEL Up to ~2700 bunches in 600 µs, repeated 10 times per second producing 100 fs X-ray pulses (~27 000 pulses/second). We want to be able to readout 1024 x 1024 pixel frames every 220 ns max bunch rate: 4.5 MHz

5. DSSC – Design Parameters

6. System Block Diagram Focal Plane • Readout Concept • Optimum analog shaping • Immediate 8 bit digitization (9 bit for f ≤ 2.2 MHz) • In-Pixel SRAM • Digitized data are sent off the focal plane during 99ms gap • Sensor & Front-end electronics can be switched off during the gaps

7. Focal Plane Overview • 1024x 1024 pixels • 16 ladders/hybrid boards • 32 monolithic sensors 128x256 6.3x3cm2 • DEPFET Sensor bump bonded to 8 Readout ASICs (64x64 pixels) • 2 DEPFET sensors wire bonded to a hybrid board connected to regulator modules • Heat spreader • Dead area: ~15% Power Module Box Board Cooling P < 27 W Chip Cooling Ladder 21 cm (1024 pixels) P < 4.5 W Signals & Clocks 256x128 Quadrant unscattered beam x-y Gap K. Hansen - DESY 128 x 256 Pixel Sensor

8. module, mechanics and power • 1-2 mW/pixel peak power  1-2 kW peak power • Power cycling about 1/100 • 10-20 W mean power • A careful thermal design is needed • Voltage regulators have to deliver a • lot of power in a short time First regulator board prototype ~3 mm K. Hansen - DESY Power Cycling all pixel electronics active during train phase, analog blocks sleeping during cooling phase

9. DSSC - Concept • DEPFET Active Pixel Sensor is the first element of the Front-end Electronics • Every DEPFET pixel provides detection and amplification with: • Low noise • Signal compression at the sensor level • High speed(fully parallel readout at 1-5 MHz)

10. Non-Linear DEPFET Working Principle gate source drain Drain current time Internal gate Charge into internal gate • The internal gate extends into the region below the source • Small signals assemble below the channel, being fully effective in steering the transistor current • Large signals spill over into the region below the source. They are less effective in steering the transistor current. • A constant charge is injected at fixed time intervals and the internal gate regions are progressively filled • In the experiment the charge is deposited at once but the DEPFET response is the same time

11. Sensor Simulations G. Lutz C. Sandow S. Aschauer PNS MPI-HLL e.g. cut clear/cleargate/gate/source  isolationinternalgate vs. clear

12. Sensor - Pixel Layout • hexagonal shape • - side length 136 µm (A=48144 µm2) • - compatible with C4 bumping @ IBM • - faster charge collection • - less split events • Pixel Options: • - Source Follower, • - Drain readout • Chosen pixel type: • - Drain Readout • technology • - 2 polySi layers • - 2 + 1 metal layers • - 12 implantations DEPFET 236 µm 136 µm 272 µm Pitchx: 204 µm Pitchy: 236 µm

13. Achievable dynamic range 8 bits 0.78mV x 256 7 bits 0.78mV x 128 1 ph @1keV  1 bin = 0.78 mV 7 bits  0.78mV x 27 = 100 mV  1245 photons 8 bits  0.78mV x 28 = 200 mV  5850 photons • The dynamic range depends on: • The shape of DEPFET curve • The number of ADC bits • The gain of the first region defines the bin size

14. DEPFET readout scheme • The signal arrival time is known • One measurement is composed of the difference of two evaluations: • Baseline • Baseline + signal • A time variant filter is used • In the real case some time must be reserved for the settling time of the DEPFET output both for : • Signal Build up • Signal clear • Less than100ns out of 200ns are used to process the signal Signal injection into the internal gate time DEPFET Drain signal current DEPFET clear Pulses Signal measurement baseline measurement readout cycle filtering process (e.g. triangular weighting function) Signal measurement baseline measurement signal settling clear DEPFET XFEL pulse XFEL pulse XFEL pulse period = 200 ns

15. Charge Collection • signal rise time • numerical simulation • cylindrical approximation • r = 136 µm • time constants • - charge collection • τ≤ 65 nsec • in drain readout the collection time is in first approximation equal to the output current rise-time charge generation at r = 0 µm, z = 270 µm charge generation at r = 110 µm, z = 270 µm

16. System noise and resolution • The noise sources of the system are: • (a) Electronics Noise: DEPFET, Analog Front-End • (b) Quantization noise introduced by the ADC • (c) Noise of the Poisson distributed Photon Generation Process • The non-linear characteristic of the DEPFET makes (a) and (b) Signal Dependent • The quadratic sum of (a) and (b) must be negligible with respect to (c):the Photon Generation Noise must be dominant

17. Electronics noise • CEQDEPFET equivalent input capacitance (decreases as the input signal increases) • a, af, b physical noise sources • A1 A2 A3 filter parameters (better for current readout) • tfilter shaping time (200ns processing time) • The noise sources are almost constant • The amplification decreases as the input signal increases • The ENC increases with the input signal amplitude From sensor simulations 55 fF... 3200 fF readout cycle Signal measurement baseline measurement signal settling clear DEPFET t t • ENC for small signals: 45 electrons r.m.s. • ENC for large signals: 2300 electrons r.m.s. XFEL pulse XFEL pulse XFEL pulse period = 200 ns

18. Quantization Noise 1 Electronics noise ADC bin size • In the linear region (small signal) there is a correspondence 1 to 1 between ADC bins and collected photons. There is no uncertainty introduced by the ADC: THERE IS NO QUANTIZATION NOISE. • Only the electronic noise counts. • We set the system such that 1ph @1 keV 1 ADC bin • We are sampling an already quantized input signal (the number of incoming photon is an integer)

19. Quantization noise 2 • For high number of photons the root mean square error (quantization noise) can be approximated by the number of photons attributed to the same bin divided by 12. • For high number of photons (non linear region) the ADC uncertainty increases and becomes dominant • The quantization noise is the r.m.s. value of the encoding error

20. Quantization Noise 4 • For high number of photons the quantization with noise with 8bits is always below Poisson photon generation noise • The total noise of the system is dominated by the Poisson photon generation noise.

21. Single photon resolution • 1ph @1keV  278 el. • ENC ~ 45 el. r.m.s. @ 5MHz • S/N ~ 6 • We place the threshold in the middle of the ADC bin • We assume the electronics noise Gaussian • The probability to detect 1 photon instead of zero is 0.1% • The probability that 1 ph signal is correctly attributed to the first bin is 99.7% • It is mandatory to have a pixel-wise gain and offset correction in order to have a correct correspondence between the first photon signals and the ADC bins • The ADC can trim offset and bin size for every pixel 0.1%

22. Noise vs. speed Operating at 2.5 MHz (acquiring a pulse every 400ns) it is possible to achieve single photon resolution @0.5keV with a S/N >6

23. dssc depfet in standard tech • 1st DEPFET withsignalcompression • DEPFETs in standardtechnologywithbasic non-linear characteristics • centralinternalgate • overflowregion • non-linear characteristics • withtwoconstantslopes • 7-cell cluster layout • Wire bonded • Available in summer 2011

24. 1st DSSC sensor production Sensor production in the DSSC techonology has started • sensor layout • 2 SDD-likedrift rings • zig-zag row-wiseconnections • irregularroutingfrom hexagonal sensorpixelstorectangularasiccells • in copperubmlayer • optional use of ubm layer as 3rd conductive layer • Implemented formats: 8 x 8, 16 x 16, 128 x 256 DSSC layout detail P. Lechner, G. Lutz PNS MPI-HLL

25. Artist’s view of Sensor / Chip Assembly Single slope ADC 200 x 200 µm by P. Fischer

26. 8 x 8 Mini-ASIC prototype 229 x 204 µm P. Fischer, F. Erdinger - Heidelberg University

27. Typical FE Measurement setup ASIC FPGA board: Programming of on-chip sequencer, global timing and synchronization. Main board: Amplifiers, MUXs, bias voltages and currents, Level translation. DEPFET Carrier board: Hold ASIC + DEPFETs (CR and SFR). Providing local filtering. G. De Vita, S. Herrmann, A. Wassatsch MPI-HLL L. Bombelli, S. Facchinetti Politecnicodi Milano

28. Readout cycle for increasing values of the input signal (single pulse). Freq = 2.57 MHz 200 mV/div 500 ns/div Gext = - 4.7 Currentstep = 635.6 nA

29. Measured weighting functions • A setup to pulse light onto the DEPFET has been put together in Milano • Can be used to inject ‘real’ signals at known times • The Weighting function of the DEPFET + Analog Front-end can be measured “A new fast filter for DEPFET readout” S. Facchinetti 13:00 A. Castoldi, C. Guazzoni Politecnicodi Milano 220 ns

30. Noise with DEPFET • Drain Readout, double integration, 1MHz operation: 13 e noise 1 MHz 13.0 el L. Bombelli, S. Facchinetti, Politecnicodi Milano

31. Noise with DEPFET • Drain Readout, double integration, 5MHz operation (50ns int.): 48 e noise 5 MHz 48.0 el

32. 8 bit ADC simplified schematic • Single Slope (Cramp~1pF, double buffering) • Ramp generated in pixel • Global Gray CodedTime Stamps @ ~1GHz • Differential distributionon coplanar wave guides • Fast latches in pixels • Gain trim via Cramp / I-Source • Offset trim with delays • More bits possible by in-pixel counting • Vref of Comp = Vref of Filter! • Comp. switches always @ same voltage & slope!!

33. ADC: Voltage → Time • INL < 1LSB (limit of current source). Can be improved further. • Charging current is adjustable in 5% steps (fine gain) • Time Jitter has- constant part of 55ps (a bit higher than expected)- Time (=signal) dependant part, as expected Slope 201ns/V

34. ADC with TX/RX • 5 MHz sampling rate. Same initial effect on INL

35. Step 1: Offset Adjustment if Noise « Bin Size: Bin Scan Zero-signal bin after offset adjustment Bin 0 Bin 1 Bin 2 CBIN0=0 CBIN1=1 CBIN2=0 Bin size Offset granularity CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=0 CBIN1=1 CBIN2=0 Upper boundary CBIN0=0 CBIN1=0 CBIN2=1 CBIN0=0 CBIN1=1 CBIN2=0 Lower boundary CBIN0=1 CBIN1=0 CBIN2=0

36. Ofsset trimming RMP Pixel Delay / Bin Shift Delayed RMP RMP

37. Offset Trim • ADC offset is trimmed via delay steps • Average delay step has been measured to 70 ps • This allows a span of 1.5 LSB (@ full speed) Error bars are from 55ps noise jitter

38. Pixel Circuit Details (up to Latches) Note that injection into arbitrary pixels is possible via injection bus! DEPFETs can be connected via Injectbus

39. ADC gain pixel comparison • Gain map of the 8x8 matrix ADC • The gain can be adjusted pixel by pixel preliminary matrix row Cap [F] preliminary matrix column J. Soldat, F. Erdinger – Heidelberg

40. ADC Trim settings • ADC gain can be adjusted pixel by pixel • In the tested ASIC there are 5 fine settings for the Ramp Current • For the final ASIC 9 settings are foreseen • Gain adjustment wil be in the 40% range • In the 9bit mode the current is reduced by a factor 2 • CSH can also be adjusted of about 10% 9 bit mode 8 bit mode ADC bin count Input voltage [V] J. Soldat, F. Erdinger – Heidelberg

41. WF measured with on chip ADC J. Soldat, F. Erdinger – Heidelberg

42. Summary & Conclusions • We are developing a Pixel Detector system for the European XFEL based on innovative non-linear DEPFET devices that constitute the first element of the Front-end Electronics • In our fully parallel readout scheme, the signals coming from the pixels are filtered, digitized and stored in the focal plane • Device and circuit simulations have shown that: • It is possible to achieve 5MHz frame readout • A dynamic range of at least 6000 Photons at 1keV per pixel is possible • A single 1keV photon resolution (S/N>6) is reachable @ 5MHz preserving the high dynamic range • Also single 0.5keV photon resolution is achievable @ 2.5Mhz • Measurements on first ASIC blocks show performance in good agreement with simulations and a noise below 50 el. r.m.s. At the maximum operating speed • First DEPFET with signal compression will be available soon • The first DSSC Sensor production comprising full-size sensors has started

43. SPARE SLIDES

44. Non-Linear DEPFET Characteristic • Output voltage (SF readout) vs. input charge (CS=0.5pF, RS=100k, ID=110mA): Lowest sensitivity: 0.05 µV/electron 220 mV for 360fC (8000 X-rays @ 1 keV) Highest sensitivity: 2.8 µV/electron ( 6.2V output swing without compression!)

45. Quantization Noise 1 • We assume not to have charge sharing among neighbouring pixels • We have to sample the output response of the DEPFET, which is: • Non linear over a high dynamic range • Discrete because the input of incoming photon is an integer • We set the size of the ADC bins equal to the output swing of the pixel given by the first collected 1keV Photon (278 el) • We have to distinguish two cases: • Very low number of incoming photons: linear region • High number of collected photons

46. Motherboard Interface to Data Generator, MS-Oscilloscope & Powersupplies Digital Power Core • DUT – Board • 4 Layer PCB • 2 different GND domains Analog Power & Input Digital Output ADC CLK & RMP Signals Decoupling Caps Pad Power Drivers Digital Power GCC & TX ADC Testsetup

47. Minimum signal Readout cycle for minimum value of the input signal (Isignal = 100 nA); waveforms are averaged. Freq = 2.57 MHz 200 mV/div 100 ns/div Gext = - 24.74 On board output variation = 124 mV On chip output variation = 5.01 mV (theoretical output = 6.21 mV)

48. ADC: 1st Test Chip • 1st ADC Test Chip: • 1 Gray Code Counter • 1 TX & 64 RX: Source-Coupled Logic • 13-mm 8-bit sCPWG pixel Timing Diagram Number of Photons 0 Max

49. 1st ADC Test Chip: Measurements • Circuit works as expected • 800 MHz operation • No missing Codes • DNL < 0.4 LSB • Rms jitter < 14 ps • Last pixel delayed by 470ps CLK……....... 800 MHz Binnom ......... 625 ps Resol. .......... 31.25 ps

50. ADC Operation • Single Slope (Cramp~1pF, double buffering) • Ramp generated in pixel • Global Gray CodedTime Stamps @ ~1GHz • Differential distributionon coplanar wave guides • Fast latches in pixels • Gain trim via Cramp / I-Source • Offset trim with delays • More bits possible by in-pixel counting • Vref of Comp = Vref of Filter! • Comp. switches always @ same voltage & slope!!