Li-Rong Zheng, Hannu Tenhunen Department of Microelectronics and Information Technology,

1. Seamless Electronic Integration- KTH Research and Education within EPROPER Program - February 2001 Li-Rong Zheng, Hannu Tenhunen Department of Microelectronics and Information Technology, IT University, Royal Institute of Technology (KTH) {lrzheng, hannu}@ele.kth.se

2. Outline Background Current EPROPER Activities at KTH Planned Research Facilities, Collaborations, and Expected Results Education Activities with EPROPER

3. Background

4. chip SCP Chip A Chip B Backplane (a) PCB Implementation (silicon efficiency ~5%) Board (b) Conventional Multi-Chip Module with bonding wire connection (silicon efficiency >25 %) Off-chip signal path ! Traditional Multi-Level Packaging Hierarchy

5. Chip B Chip A Feature size Silicon: in um and sub-micron, Packaging: in mm and sub-mm Impedance discontinuity, Signal integrity, Simultaneous switching noise (SSN)!!! Parasitic C L Silicon: fF, pH; Packaging: PF, nH Speed: on-chip: ~GHz, off-chip: <500M system: <300 MHz Power Consumption core: ~(50%-70%)Ptotal off-chip driver: ~(30-50%)Ptotal Silicon Real Estate logic core: ~(50%-70%), off-chip driver: ~(30%~50) Extra silicon area for large off-chip driver; Cost, size etc. Degraded off-chip/ system performance Extra power consumption for off-chip driver; Thermal, mechanical etc. Bottleneck of Electronic Package: a system view

6. Bottleneck of Multi-Level Package: Summary Power Consumption: in a modem microprocessor, 60~70% total power consumed on global buses, I/Os, clock distribution Simultaneous Switching Noise [Ldi/dt]: in a 80W 2.5V CPU chip, di/dt= 64GA/s. If a package pin has a typical Lpin=1nH and DVmax< 10%Vdd , the required number of power I/O pins will be >256 !!! Degraded Off-Chip Speed: On-chip speed of a CPU chip is in GHz, off-chip <200MHz! Signal Integrity: Impedance Discontinuity, Package pins behave like low-pass filters and stop the high frequency signals Expensive Chip Area: Many chips are package pin limited due to large size of bonding pads, very larger off-chip drivers also occupy a large amount chip area. Typical area: 30~50% for I/Os, and 50~70% for logic cores

7. “The Ultimate Electronic Package Configuration will be the Disappearance of Package !!!” -- Nasser Greyali, Director of Assembly Technology Development, Intel Corp, (Oct. 2000) Seamless Integration Source: PHILIPS with some modification according to ITRS’99 (Internal Technology Roadmap for Semiconductors, 1999 Edition ) System-in -Package (SiP)

8. It’s not just a shrink in size, and more important, it provides: • Very High Performance • (shorter chip-to-chip interconnections, and reduced parasitic effects e.g. Lpin =5nH in PLCC and Lpin =9pH in flip-chip) • Broadband • (Shorter chip-to-chip interconnections and better impedance control, higher I/O pin count, higher data throughput per pin ) • Mixed-Signal Integration • (e.g. Digital /analog/RF, silicon/SiGe/GaAs technologies ) • Lower Power • (save power 10~50% !, due to reduced off-chip driver requirements ) • Others • Reduce Cost: save expensive chip real-estate by reducing off-chip drivers: • Lower Switching Noise (Ldi/dt): e.g. Lpin =5nH in PLCC pin Lpin =9pH in flip-chip bump • Applications: • Mobile terminals, communication links, PDA, and high- performance computers From TH-PCB package to SMT-PCB package to MCM integration

9. Seamless Electronic Integration Means: • Technically, to close the gap between packaging chip, such that we are able to achieve orders of magnitude improvements in size, cost, functionality, and overall system performance, as well as low power • Physically, to develop an integrated unified electronic system that is optimized by efficient chip/ packaging/ system co-design with considerations of electrical/ thermal/ thermo-mechanical effects in a self-consistent manner • e.g. Single-Level system-in-package integration (chip-first, chip-last), silicon-on-silicon, wafer-level package with embedded passive components and/or thin chips • Key Fundamental Technologies: flip-chip technology, single-level chip integration, embedded passive elements, microfabrications From chip/system design perspective, it is really necessary to integrate future electronic systems towards seamless integration. This we can see a similar transition as going from discrete devices to integrated circuits and we expect, if this transition is successful, a similar impact on electronics as the integrated circuit has had up to today

10. Seamless Electronic Integration: example (GIT, Atlanta) SLIM: A chips-last system integration approach which is under cultivating at Packaging Research Center, Georgia Institute of Technology

11. Seamless Electronic Integration: example (Fraunhofer Institute, Berlin ) Thin chip integration has ultrathin chips integrated in the redistribution layer of a larger chip. (Source: Fraunhofer IZM)

12. RF/Analog chips Memory AD/DA Control Unit DSP Power and Ground Distribution Layers Signal Wiring Layers off-chip interconnect layer I/O Substrate (Si,Ceramics) Dielectric(SiO2, low k) chip Seamless Electronic Integration: example (KTH, Stockholm) Single-Level Integrated Packaging (SLIP) -- an extension of VLSI technology • Unique Features: • IC backend Process • Ultra high package density • Mixed signal integration • High performance • Good pad driver capability • Low power • Weight, size, cost etc SLIP - a chips-first seamless electronic integration approach being under development at KTH. Test samples have been made during 1999~2000 (using VLSI process + low k dielectrics)

13. Current Research Activities

14. sample holder sample holder chips polyimide substrate vias Al metal Silica xerogel Research Activities: single-level integration packaging Process Sequence for SLIP: with VLSI Processes (c) Polyimide cure and sample holder removal (a) Back surface polishing (b) Substrate bonding (d) Multi-layered silica xerogel deposition and planarization (e) RIE via-hole etching and contact-via deposition (f) Metal film deposition and interconnect pattern . SLIP fabrication steps. Repeating steps (d) to (f) makes multi-layered interconnections

15. Planarization Technique: Multi-Layered Spin-on Coating Precursor: TEOS + water (catalysis) Solvent: Ethanol Spin rate: 1000~5000rpm Cure: 350~400oC 15min Number of layers: 10 Total thickness ~ 10mm er=2.2, tan(d)= 0.02 @1MHz

16. Test modules for Single-level Integrated Package 5 mm 5 mm

17. HF Properties of Package and Interconnects :Modeling & Measurement Measurement: HP 8510A (45M-20GHz) On-chip G-S-G probe SOLT calibration, Y-parameter de-embed of pads Reference Impedance Transformation:

18. SiO2 Si-substrate Research Activities lInterconnect Parasitic Extraction Tools: FEM, FDTD, MoM, and PEEC q3(2)D Numerical Simulation Accuracte, Time and memory consuming, Inefficient for full chip extraction Neumann boundary conditions at metal and substrate edges The equation is solved by Finite Element Method Figure: 3D Interconnect Capacitance Extraction for an SRAM Cell

19. Technology description file Wire parameter: w, d, metal layer etc 2D field solver: Cm, Cg Curve fitting: Empirical formula: Cm, Cf, Cf’, b~F( w,d,h,t) 3D capacitance Inductance extraction t h Cm d w Skin effect resistance Substrate Cf Cp Cf’ Cf’ Cp Cf’ Cf’ Cp Cf A Parameterized Interconnect Model

20. Vdd L Vdd p pwr Switching Core on gnd Vss Vss L p Power Distribution and Synthesis Vdd Vin Vss • L.-R. Zheng: Efficient and Accurate Modeling of Power Supply Noise on Distributed LRC On-Chip Power Network, IEEE ISCAS 2000

21. System level power delivery network High-Frequency on-chip global and semi-global lines Impedance (ohms) 0.025 0.020 0.015 0.010 0.005 0.000 High-Frequency Chip on SCM/MCM Mid-Frequency SCM/MCM on Board 1999 Target Impedance Low-Frequency Power Regulator 100 101 102 103 104 105 106 107 108 109 1010 Frequency (Hz) Why power distribution? -- a packaged system view

22. Packaged ULSI Power Distribution: Challenges A capacitor chip is bonded to an Alpha 21264 processor chip to provide power conditioning • Extremely large size of the network • Millions and hundreds millions of nodes typically, SPICE simulation: >>3 months • Complex structures • Topologies: meshes, trees, rings, planes, I/O distribution: peripheral edge, area array connection etc • Many unknowns at early design stages • Decision about structure, size, layout, and package parameters must be made at early stage • Parasitic, current profile of each block are not known until very end of the design cycle Problems revealed at post-layout stage are expensive to fix Design of on-chip decoupling capacitor is complex

23. Equivalent Circuit Model of Power Grid Modeling of a meshed power grid with a chain of p-type equivalent circuits. CLp: switching load capacitance(clock cycle dependent) , extracted from gate level power simulations Cp-1,p=Cw,p+Cm,p+Cqp withCw,p: wire self capacitance Cm,p: mutual capacitance between Vdd and Vss Cqp: sum of load capacitance of quiet gates (symbiotic bypass capacitance)

24. Peak Noise Formulation for an Arbitrary Node in an Arbitrary Grid CLj: switching capacitance at node j Basic idea: switching charge

25. m m+1 4 5 6 1 2 3 i j Peak Noise Formulation for Arbitrary Power Grid We can write the noise equation (with total n nodes) in matrix form as: Free (unknown potential ) nodes: 1,2,3,…m-1,m Prescribed (fixed potential) nodes: m+1,m+2, n Or in a submatrix form as

26. Package inductance 2pF decaps Concurrent Design Example: Decoupling Capacitor Design before decap • Sketch of a 10 by 10 power grid with four external supply connections. X: 150mm/grid, Y: 100mm/grid after decap • Comparison of peak noise before and after decoupling capacitors placement. CPU time: in our tool is 0.06 second , whereas in HSPICE it takes >25 seconds

27. Impedance (ohm) One fat Vdd-Gnd pair with w=64mm, d=48mm 40 small Vdd-Gnd pairs with w=1.6mm, d=1.2mm Frequency (Hz) Self-Decoupling Power Distribution Output impedance of power lines with various cross sections and line lengths. Measurements

28. Vdd pins Vss pins o Vn=150mV * Vn=300mV f=30% f=20% f=10% average current constraint Power Distribution & On-Chip Decoupling • Area Array Connection Power/Ground Pin Distribution for External Supply • Self-Decoupling between Vdd and Gnd An example of required minimum number of power/ground pin pairs in per cm2 chip area as a function line pitch width for power distribution, where Vn represents allowable noise margin and f represents a switching factor in the chip.

29. Current Research Activities @KTH (summary) Single level integrated packaging module study Material deposition, Spin-on coating, Planarization technique, Metallization and Interconnection pattern by life-off process Electrical design, modeling and measurement (45MHz~20GHz) Mixed-signal coupling and digital signal integrity 3D full wave analysis of interconnection and package HF Interconnect measurement and modeling from measurement Interconnect delay and crosstalk analysis under deep submicron constraint Power distribution and on-chip decoupling strategy research Unified chip/package irregular power grid modeling and simulation Nose reduced power distribution with self-decoupling and area array I/O Chip/package co-simulation for power distribution and signal distribution Passive devices and effective antenna (smart antenna structure) for compact systems Target to mixed-signal integration with digital and analog/RF

30. Publications in 2000 (1) Li-Rong Zheng, Hannu Tenhunen: “Single Level Integrated packaging Modules for High Performance Electronic Systems, ” in proc IEEE 50th Electronic Components and Technology Conference,pp.1460-1466, 2000 and was invited to submit to IEEE Trans. Advanced Packaging for a Special Issue (2) L. R. Zheng and H. Tenhunen. “Fast modeling of core switching noise on distributed LRC power grid,” in Proc. IEEE 2000 Electrical Performance of Electronic Package Meeting, Scottsdale, Arizona, USA, Oct. 2000 and was invited to submit to IEEE Trans Advanced Packaging for a Special Issue. (3) L.-R. Zheng and H. Tenhunen. “Single level integration packaging: meeting the requirements of ultra-high density & high frequency,” accepted by Journal of Electronics Manufacturing, 2000 (4) Li-Rong Zheng, Bingxin Li, Hannu Tenhunen: “Efficient and Accurate Modeling of Power Supply Noise on Distributed On-chip Power Networks”, in proc IEEE International Symposium on Circuit and System, pp.II 513-516, 2000 (5) Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: “Accurate A Priori Signal Integrity Estimation Using A Multilevel Dynamic Interconnect Model for Deep Submicron VLSI Design” in Proc 26th European Solid-State Circuit Conference, Stockholm, Sweden, Sept, 2000 (6) L. R. Zheng and H. Tenhunen. “Design and analysis of power integrity in DSM SoC circuits,” in Proc. IEEE 2000 Norchip Conference, Turku, Finland, Nov.2000. (7) Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: “Combating Digital Noise in High Speed ULSI Circuits Using Binary BCH Encoding” in Proc. IEEE International Symposium on Circuit and System (ISCAS’2000), pp.IV.13-16, 2000 (8)Bing-Xin Li, Li-Rong Zheng, and Hannu Tenhunen “An Improved Settling Model of Swithed-Capacitor Integrator for High Speed Sigma-Delta Modulator Simulation,” in Proc. IEEJ 2000 (4th) International Analog VLSI Workshop,June 2-3, 2000, Stockholm, Sweden (9) L.-R. Zheng, and H. Tenhunen, “Efficient modeling, analysis and design of power grid for CMOS ULSI circuits ” submitted to IEEE/ACM Design Automation Conference, Las Vegas, 2001 (10) L. R. Zheng and H. Tenhunen “Global interconnect design for high speed ULSI and SoC,” presented in EDA-Traff 2000, Design Automation Conference, Kista, Stockholm, Sweden, April 2000.

31. Planned Research Focus and Research Team

32. KTH's Focus • Seamless Integration Technology • Wafer-Level Packaging with Embedded Passive Components • Single Level Integrated Packaging Modules • Aims of experimental work mainly are • (a) experimental verification of simulations • (b) “extension” silicon technology to package technology • Seamless Modeling and Simulations for the Package Modules • Chip/Package/System co-design and simulation • embedded passive elements, unified chip-package interconnection modeling, seamless on-chip and off-chip routing, novel circuit and system architectures with seamless technologies for clock and power distribution, system buses, high speed and low power off-chip signaling techniques, system partitioning and system timing, with emphasis on early estimation • Mixed-signal coupling and digital signal integrity • Unified electro-thermal modeling and measurement

33. Importance of Future Passives Integration In RF Circuits In Digital Circuits The number of passives is significant in digital (non-RF) circuits, especially for the suppression of line noise and electromagnetic interference (EMI) This chart (made available from Nokia) illustrate the decrease in ICs and passives in the RF section of a GSM phone from 1994 to 2000 Source: Wireless System Design, Feb. 2000

34. Decoupling Capacitor High-Q Inductance Dielectrics (10~20mm) Passive dielectric (1~2mm) Global interconnections (on-chip) Silicon chip ( off-chip) Decoupling Capacitor High-Q Inductance Power distribution Signal distribution RF IC Digital IC Digital IC Analog IC Dielectrics (10~20mm) KTH Focus 1: Seamless Integration Technology 1. Wafer-level packaging with passive components and optimized seamless off-chip interconnections for long on-chip communications 2. Single Level Integrated Packaging Module: continue our previous research, with emphasis on embedded RF components and applications such as in a Bluetooth Module and Wireless LAN (WLAN) module. Base-Substrate

35. DSP PCI Timer ROM RAM RISCMPU Ethernet Controller Memory Controller API SSP UART Watchdog bridge IP modules SSP SSP DSP RAM Loop filter VCO SSP API ROM Radio ASIC Balun Antenna Filter Switch Custom modules RF components RISCMPU Memory Controller Antenna Filter Ethernet Controller Switch System-in-package design example: co-simulation and system partitioning PCI VCO bridge Balun Radio ASIC Loop filter UART Timer Watchdog Focus 2: Seamless Modeling and Simulations • The aim of this study is mainly to find out the impact of package parasitic effects on • (1) Signal transmission and signal integrity; • (2) System-timing and system performance; • (3) Chip I/O design and power distribution; • and hence • (4) Optimized system partitioning and system performance

36. Aim of the Project • Key technologies for seamless integration is emerging or has emerged, • aim of this study: • Bring a new view of system integration (other than an incremental technology improvements) that enables new levels of integration both in system complexity and in technology fusion; • Evaluation of the new technologies (both challenges and opportunities) for seamless integration systems, with regard to integration density, thermal characteristics, electrical performance, signal integrity, and particular applications; • “Extension” of silicon technology to package technology for seamless integration; • New design space exploration for such integrated systems in a unified chip-package-system co-design manner with emphasis on high performance systems and efficient design techniques.

37. Supervisor: Prof. Hannu Tenhunen Electronic System Design Co-Supervisor: Prof. Mikael Östling, Electronic Device Technology Senior Researcher: Li-Rong Zheng (Start from 05/01) Background: Package and Mixed-Signal System Design, Material and Thin Film Technology Senior Researcher: Carl-Mikael Zetterling Background: Power Electronics, RF and HF VLSI and Thin Film Technology Ph.D. Student: Mr.Wim Michielsen EPROPER student(99/00) Industrial student (00/01-) Ph.D. Student: Mr. Meigen Shen From Eastcom Ltd. (05/01) 4y industrial experience in communication system design Ph.D. Student: Mr.Xinzhong Duo From Osaka University, Japan (05/01) 4y research experience in thin film and devices (silicon-silicon bonding ) Ph.D. Student: Ms. Wei Liu student at EKT, background in transient thermal modeling of combustion processes Seamless modeling and simulation, system/ package/ chip co-design, signal integrity Transmission line modeling, EMC/EMI, Material and processing, electrical measurement Thermal and electro-thermal modeling, thermal measurement and verification Bluetooth Radio RF components (Seamless Electronic Integration) /(System-in-Package)/ (e.g. Bluetooth/WLAN) KTH’s New Team in EPROPER

38. Student Projects • 1. Wafer-Level Packaging and Single Level Integrated Packaging Modules for High-Frequency Wireless Communication Devices • Research Content: subject 1, part of subject 2 • Participants: • Senior Reseracher: Li-Rong Zheng, Carl-Mikael Zetterling, • Ph.D. Student Xinzhong Duo, ESK/KTH • 2. Concurrent Packaging and VLSI Design for High-Frequency Circuits and Systems • Research Content: subject 3, part of subject 2 • Participants: • Senior Researcher: Li-Rong Zheng • Ph.D. Student: Meigen Shen, ESK/KTH 3. Unified transient thermal modeling of heat dissipation in high performance electronics Research Content: subject 4, part of subject 3 Participants: Senior Researcher: Carl-Mikael Zetterling, Li-Rong Zheng, Ph.D. student: WEI LIU

39. Research Subjects: • 1. Seamless package and integration technologies and experimental verifications • Wafer level packaging (WLP), single level integration package (SLIP) technologies (System-level and mixed-signal package, with digital, analog, and RF together), with emphasis on embedded components such as decoupling capacitors, integrated inductance, and embedded antenna in WLP and/or SLIP • Novel materials, substrates, and metallization technology and their high frequency characteristics • Seamless on-chip and off-chip interconnection technology such as in WLP and SLIP for global on-chip communication, area array connection • High frequency measurement and experimental verification for design and simulations • 2. Signal transmission and signal integrity analysis • Impact of deep submicon chips on signal integrity issues for packaging and board • Mixed-signal coupling issues for system-in-package and system-on-chip package • Electromagnetic full-wave simulation of broadband interconnections, interconnect parasitic extraction, passive components modeling and experimental verification • Effect of impedance discontinuity on off-chip signal transmission and coupling • Novel high-speed and low power off-chip signaling techniques and their opportunity in seamless integration • Power delivery, power impedance control and on-chip/off-chip decoupling design • High-speed data bus design for seamless chip-board communication, high-speed signal distribution • EMC and EMI problems for package and system • Signal integrity measurement and model development based on measurement • Noise rejection techniques and noise measurement • Based on the above studies, develop a unified 3D interconnect modeling or library from chip to package to board-level

40. Research Subjects: (continue) • 3. Concurrent packaging and VLSI/ULSI design • Performance analysis for system-in-packaging and system-on-chip integration, system level view of integrated chip, package, and substrate needs analysis • (Impact package on chip performance and cost, chip area, power consumption, off-chip speed etc, early stage system estimation including packaging effect) • System-level power distribution strategy, power delivery (board, package, and on-chip) analysis and co-design. • (e.g. early stage estimation of power/ground pin number, power noise estimation, pin assignment, area array power connection or peripheral connection, power impedance control, decoupling design) • System-level clock distribution strategy with emphasis on GHz on-chip and off-chip • (e.g. new clock distribution topology and technology such as skewless clock distribution with standing waves, distribution on-chip clock using off-chip interconnections and/or clock chips in a package module etc.) • System-level signal distribution analysis and chip/package/system co-design • (e.g. using high speed off-chip interconnections to replace long on-chip global wires ) • Thermal management for clock and power distribution with unified chip-package model, system-level electrical-thermal co- simulation • (thermal heating and thermal transient, 3D thermal distribution, impact of thermal effect on power distribution of the system ) • 4. Unified transient thermal modeling of heat dissipation and transfer • Heater generation and self heating modeling in semiconductor chips • 3D physical simulation of heat dissipation and spreading in package module (spatial domain), thermal transient simulation (time domain), and impact of metal wires on these properties • High-level and early stage seamless electrical-thermal co-simulation, e.g. thermal simulation with high-level hardware description language such as VHDL as input • Modeling verification and electrical-thermal measurement • Development of high resolution thermal imaging system for thermal mapping in package and chips

41. Internet Office Ethernet HiperLAN module: Intarsial 2.4GHz VCO: Intarsia Blutooth module: Ericsson Application Area: For example, highly miniaturized and high performance electronic systems such as short distance communication based appliances and personal devices

42. Facilities, collaboration, and expected Results

43. Equipment & Facilities • Software Program: • 3D full wave electromagnetic simulation (HFSS), HP-moment (HP-Ads) etc. • Full license from Mentor Graphic (including package and PCB design, Interconnect Synthesis, IS, high-level design and synthesis tools) • A number of other circuit and system simulation-tools from such as Agilent, Cadence, Synopsys (a complete set of CAD tools from system-level, gate-level, transistor-level, and layout-level design) • Several in-house developed tools and algorithms (LRC extract, power distribution, interconnect post-processing, system-level interconnect simulation etc.) • Device and process simulation tools from Avant!, Silvaco and ISE, which allows electrical, magnetic and thermal simulations in 2D and 3D ( External circuits are also possible) • Equipment: • Several HP network-analyzers (20GHz and 60GHz), probe station, TDR(20GHz) measurement, BER measurement, DC (20fA, 1mV) • Thermal imaging system is going to be set up by other students at EKT • KTH clean room with full access collaborated with EKT • KTH Clean Room • Equipped with a complete line of facilities for semiconductor processing, package and assembly, providing for research projects in KTH and ACREO. (e.g. various facilities for thin film deposition and lithography, thermal processing, device mounting, and flip-chip bonding)

44. Electrical Characterization, EKT/KTH

45. PECVD RIE Sputtering Lithography Evaporator Wet chemical furnace polish spin KTH Facilities (example)

46. Collaboration Our specialized competence (summary): Very Experienced in Chip and System Design Currently working on: system-level, algorithmic level, logic level, circuit-level, and physical level designs Most of research projects are currently going with these different design levels, with focus on system-on-chip, mixed-signal systems, ADC/DACs, DSP, Low Power ICs, High Speed CMOS ICs, and RF ICs. Competence in Modeling and Simulation of Electronic Package LRC parasitic extraction with full wave analysis ( FEM, FDTD, MoM, PEEC) Professional CAD platforms and a design team consisting of physical level, circuit level, logic level, chip-level, package and system level Knowledge in advanced signaling standard, system buses, logic families, signal integrity and system timing issues, signal and power distribution Skills in Silicon Technology and HF Electrical Measurements A complete set of silicon processing line for research, from material deposition and photolithography, to package and assembly Facilities and expertise in electrical measurement (Scattering parameters, TDR, BER, current in 20fA, Voltage in uV)

47. Collaboration • With MH: • Verification of designs with different simulation tools • Test structures implemented in our Silicon Technology • Electrical measurements • With CTH: • Electrical performance characterization for CTH’s substrate and interconnect materials, • Test CTH’s solder bumps in our WLP and SLIP modules • Thermal modeling and thermal measurement • With LiTH: • Simulation and measurements of electrical performance of interconnections and passive components using LiTH’s dielectrics and conductive materials • Performance and cost analysis for system-in-package and system-on-chip • Effects of non-linearity of dielectrics on signal propagation and signal coupling • We can also assist LiTH in device and circuit design in polymer electronics • And more: • Particular interests from other University are very welcome • Aim is to combine the specialized competence for each university and share the facilities, in order to achieve high-quality research and education • EPROPER research workshop could be arranged, more possible collaboration can be discussed between EPROPER students and researchers

48. Education Activities

49. EPROPER Graduate School EPROPER Courses at KTH : • Electronic System Packaging, 5c (SoC Master) • Digital System Engineering, 5c (undergraduate students) • Mixed-Signal System Design, 5c (2B5457) • Physical Architecture Design for VLSI System, 5c (2B5456)

50. Objective: New competence profiles needed for EE • Deep sub-micron effects require that future chip and system designer/team has knowledge on physical level design issues • The increasing complexity of electronic systems and system noise problems require to explore new design space with unified physical/functional/methodology views. Challenge: New breed of students than our generations