1 / 19

VIPIX, pSuperB, (SuperB) Atlas/FTK

VIPIX, pSuperB, (SuperB) Atlas/FTK. M. Villa 04/11/2010. VIPIX (2009-2011). Sviluppo di sensori a pixel in integrazione verticale High bandwidth High rate (100 MHz/cm 2 ) Data push Time identification 100 ns Spatial resolution 12 um Low budget material (<<1 Xo)

tilden
Télécharger la présentation

VIPIX, pSuperB, (SuperB) Atlas/FTK

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. VIPIX, pSuperB, (SuperB)Atlas/FTK M. Villa 04/11/2010

  2. VIPIX (2009-2011) • Sviluppo di sensori a pixel in integrazione verticale • High bandwidth • High rate (100 MHz/cm2) • Data push • Time identification 100 ns • Spatial resolution 12 um • Low budget material (<<1 Xo) • Caratterizzazione dei sensori su fascio • Trigger/DAQ • Memorie associative

  3. Prospetto architetture e sottomissioni Nomi Indicativi prossime sottomis-sioni Sensor Technology Readout architecture core version • Caratteristiche ed innovazioni introdotte nelle varie architetture: • 1 : AREO (Apsel family Read Out) • Apsel family read out • MP management logic • Parallel hit encoding • Sparsified column readout • 2 : SORTEX (SORTed EXtraction) • Time sorted hit extraction • horizontal parallelization (submatrices) • zone sparsification / output compression • I2C-like interface • 3: SQUARE (Sequenced QUery Advanced REadout) • No MP • Matrix TS query for time sequenced readout • Single column parallel sparsified readout (higher efficiency) • higher Time Resolution (more robust time sorting for short BC) Mixing interdetto

  4. Layout sottomissioni con readout APSEL4D APSEL3D Type MAPS Techn. STM 0.13 Matrix 32x128 Type MAPS Techn. STM 0.13 Matrix 8x32 2006 APSEL3D _TC 2007 Type 3D MAPS Techn. Tezz. C. 0.13 Matrix 8x32 2009 NP!! FE4D32x128 alias SuperPX0 TypeHybrid Techn. STM 0.13 Matrix 32x128 Architetture scalate per matrici di dimensioni ridote 2009 arrivato ieri 4 (Più o meno in scala fra loro)

  5. 12-05-2010 Beam axis 1-3 mm 0.5 mm 0.25 mm Piste data line di 2 sottomatrici Piste data line di 2 sottomatrici 0.16 mm 0.16 mm 12.8 mm Submatrix 4 256x192 pixel matrix 50 mm pitch Active area=128mm2 Readout=10-30mm2 Area~3xarea from FE32x128 Submatrix 3 10 mm 10.56 mm ~ 75 Pad – pitch 130 mm ~ 75 Pad – pitch 130 mm ~ 75 Pad – pitch 130 mm Submatrix 2 Submatrix 1 0.120 mm cut line 14.79-16.79 mm Chip dimensions for Layer0 pixel module Produrremo un ritaglio!

  6. Piste data line di 2 sottomatrici Piste data line di 2 sottomatrici 0.16 mm 0.16 mm ~ 38 Pad – pitch 130 mm Chip dimensions for APSELVI 128x96 Chartered/Tezzaron 6-07-2010 Beam axis 1.6 mm 0.5 mm 0.25 mm 6.4 mm Submatrix 1: 128x48 128x96 pixel matrix 50 mm pitch Active area=32mm2 Readout=8mm2 Area~x2x area from FE32x128 5 mm 5.56 mm ~ 38 Pad – pitch 130 mm ~ 38 Pad – pitch 130 mm Submatrix 2: 128x48 0.120 mm cut line 8.99 mm

  7. Parallelamente…. DAQ: EDRO V2 • Born as a SLIM5 DAQ board • Recycling several boards: CMS muon trigger mezzanine, VME, CMS barrel sorter, S-Link & TTCrq • Used happily in beam tests • Reused in ATLAS as the LUCID DAQ board: • Bunch-by-bunch luminosity evaluation • Next use: • ZDC luminosity measurements • VIPIX DAQ • Vertical Slice “DO” board Can interface with an Associative Memory board for triggering purposes

  8. VIPIX DAQ duties Obbiettivo principale: Test beam settembre 2011 • Installare in gennaio-giugno tutta l’infrastruttura di beam test a Bologna: • 4 piani strip; 4 scintillatori; • 2 maps digitali (Apsel-like) + 1 analogico • 1-4 MAPS Perugine (RAPS) • 1 chip MIMOROMA3

  9. pSuperB: progetto pilota SuperB (R&D only) • Coinvolgimento di Bologna sulle tematiche del vertex detector: 80-90 % overlap con VIPIX • Chip di lettura • DAQ Elevate sinergie con il PRIN 2009 se verra’ approvato

  10. The SuperB Silicon Vertex Tracker Can use Babar SVT design for R>3cm Reduced beam energy asymmetry (7x4 GeV vs. 9x3.1 GeV) requires improved vertex resolution Layer0 very close to the IP (R~ 1.5 cm) with low material budget Background levels depends steeply on radius Layer0 needs to have fine granularity and radiation tolerance Bp pdecay mode, bg=0.28, beam pipe X/X0=0.42%, hit resolution =10 mm 20 cm 30 cm 40 cm Dt resolution (ps) MAPS (2 layers) Hybrid Pixels (single layer) • BaBar SVT • 5 Layers of double-sided Si strip sensor • Low-mass design. (Pt < 2.7 GeV) • Stand-alone tracking for slow particles. • 97% reconstruction efficiency • Resolution ~15μm at normal incidence old beam pipe new beam pipe Layer0 • Layer0 subject to large background and needs to be extremely thin: • > 5MHz/cm2, > 1MRad/yr, < 1 %X0

  11. R&D on strip/pixel options • Layer0 with striplets (technology mature but need some work): • Readout chip! (totally missing) • Module assembly with multilayer fanout (still uncovered !) • HDI/transition card electronics (partly covered by M.Citterio assuming similar to pixel option…not enough!) Hybrid pixel: • Prototype Front-end chip for hybrid pixel (32x128, 50 um pitch) tested • Results in fair agreement with simulation • Pixel sensor matrix produced and tested: good quality • FE chip + sensor matrix bump-bonding in june and test in lab in September CMOS MAPS: • Pixel readout architecture for next matrix (3D MAPS with 2 CMOS layers interconnected, ~Dec 2010) could work in data push and triggered mode • triggered readout reduces pixel module complexity (lower speed for links & less material for pixel bus)

  12. DAQ reading chain for L0-L5 HDI +Transition card+FEB+ROM DAQ chain independent on the chosen FE options Pi+Bo+Bg/Pv Milano Bologna Frascati, 28/09/10 12

  13. ATLAS/FTK • Progetto di tracking veloce in ATLAS basato sulle memorie associative • Si dovrebbe collocare tra il primo livello di trigger ed il secondo. E’ denominato L1.5 • “Feature extraction on L1 data” • Approvato in ATLAS in primavera • 2 Steps: • 2012 Vertical-slice test (parassitaggio su un quadrante) • 2013… Installazione su tutto ATLAS Siamo coinvolti Ci vogliono ma non abbiamo dato la disponibilita’ per ora

  14. FTK Event selection –trigger • LHC frequency 40 MHz • Events frequency on tape/disc 100 Hz • Selection is necessary • 3 trigger levels • first level (HW) • HLT (SW) • second level • Event Filter • FTK: HW processor to reconstruct charged tracks at LVL2 • Pt>1 GeV • Inside the whole ID • ~off-line quality Works in parallel with DAQ Can be added even after the data taking has began Francesco Crescioli

  15. Fast Tracker – Struttura interna • Ricieves hits from DAQ • ComunicateswithAssociative Memory boards • Sends hits &found roadsto the Fitter • 6 boards in parallel • Each DO handles 1-2 layers • Performs pattern recognition on Super Bins • Send back found roads to DO Struttura modulare Piu` processori possono lavorare in parallelo E` possibile iniziare con una versione prototipale e poi aggiungere EDRO in Vertical slice Roads and hits with high risolutionare composedand the Linear Fitis executed to select real tracks, stored in a buffer ready for the LVL2 CPUs Francesco Crescioli

  16. Guadagni con FTK • Miglior rapporto segnale/fondo; migliore capacità di discriminazione ai livelli di trigger bassi maggiore statistica finale Bs→μμ Results (CDF – ATLAS – ATLAS + FTK) • CDF with 780 pb-1of data 16/3/2006 • BR < 1.0x10-7 @95% CL • ATLAS (2006) • LVL1 2 muons Pt>6 GeV • 30 fb-1 21 B events 60 Backgr. • BR < 6.6x10-9 @90% CL • ATLAS + FTK • LVL1 singolo muone Pt>6 GeV • 30 fb-12ndm Pt>6 GeV 66 events (|η|<1 prototype) 178 events (|η|<2.5|) background LVL2 Rate for 2ndm Pt>3 GeV O(10Hz)

  17. Joint venture • Vertical Slice: • Pisa: AM board aggiornata • Americani: Interfaccia vs rivelatori a Pixel • Frascati: ricezione hit e clustering (EPMC) • Bologna: Data organizer (firmware/software) Elevate sinergie con il PRIN 2009 se verra’ approvato

  18. Mezzanina ricezione hits • Compatibilita’ EDRO; • Usabile anche per SuperB • Progetto finito; produzione 10 pezzi a breve

  19. Riassumendo • Impegni certi: • VIPIX: sviluppo architetture RO, layout 2 chips • VIPIX: test beam 2011 – Software/firmware • pSuperB/SuperB: sovrapposizione VIPIX • ATLAS/FTK: commitment fino alla vertical slice (2012) • ATLAS/FTK: sviluppo software e firmware (Ing. Ele.) • Impegni possibili/da decidere: • ATLAS/FTK oltre il test del 2012 • SuperB (se approvato) quante forze? • Oltre il 2011: continuazione di VIPIX? • Impegni probabili: Prin2009/Vipix+FTK-like • Impegni chiusi: Prin2007

More Related