6. Basic Machine Organizaton

1. 6. Basic Machine Organizaton 6.2 Computer Organization Computer Studies (Advanced Level)

2. Computer Organization • A computer has no intelligence. It follows the commands you specify in the program. • Program: • A sequence of instructions. • The CPU executes them one-by-one.

3. Programming Language • Machine-Level: • used by the computer • trains of 0’s and 1’s • Assembly level source code -> assemble -> object code • High-Level and Mid-Level • Nearer to natural language • Need compilation • Source code -> compile -> object code

4. Why Assembly Language? (1) • Machine program is difficult to write, debug, understand and error-prone. • Use symbols or mnemonics to replace the 0’s and 1’s. E.g.: • assembly : MOV A, 1 • machine : 0011 0101 0001 • Using machine language, one has to determine the address of “A” manually.

5. Why Assembly Language? (2) • Using Assembly Language, you need an assembler to translate an assembly program to a machine program. • Assembly Language • 1-1 correspondence with the machine program. • Directly communicates with the computer • has precise control of the computer • machine dependent

6. Computer Architecture Disk Modern CRT terminal Keyboard Memory (RAM, ROM) Processor I/O Unit Control Data Address

7. Processor • ALU (Arithmetic Logic Unit) • system clock • registers • Instruction register(IR) • Instruction decoder(ID) • internal system bus

8. Bus and register Control System Bus Data Address Controller(System Clock) MDR (Data Buffer) MAR(Address Buffer) ID CCR Registers Program counter(PC) InstructionRegister(IR) ALU Internal Bus

9. Basic Instruction Formats • An instruction is divided into different fields: • Opcode: Operation to perform, e.g. addition • Operand 1 to Operand N: The data which the operation will act on. Opcode | Operand 1 | … | Operand N

10. Basic Instruction Formats • The number of operands N varies for different computers. In 8088, N can be 0, 1, or 2. • N=2: • E.g. “ADD AX, BX” means “AX<-(AX)+(BX)” • Note: “(AX)” means the content of the register “AX” • N=1: • e.g. “PUSH AX” means “Stack <- (AX)” • N=0: • e.g. “RET means return from procedure

11. Instruction Execution Cycle • 1. Instruction Fetch • a) The address of the current instruction to execute is stored in a CPU’s internal register called the Program Counter (PC). (much like a “pointer” to point at the next instruction) • b) Put this address into Memory Address Register (MAR) and initiates a Read Cycle. • C) The instruction is read into another CPU’s internal register called the Memory Data Register (MDR). • D) the data in MDR is then forwarded to the Instruction Register (IR) via the internal bus. • Note: MAR = Address Buffer, MDR = data buffer

12. Instruction Fetch • e) at the same time, PC is incremented to point at the next instruction:

13. Notes of Instruction Fetch • Note: • Increment PC by how much? • It depends on the size of the current instruction (what if irregular) • Assume the next instruction follows the current instruction. (What if we have a branch instruction? E.g.if (A>0)…else…

14. Instruction execution cycle • 2. Instruction Decode: • Generate the control signals to accomplish the tasks of the instruction. • 3. Data Fetch (for operands)

15. Instruction Fetch - Execution • 4. Execution: • ALU • Set the condition codes (flags) to indicate the characteristics of last execution’s result. • E.g. overflow, negative

16. Execution • Note: • Condition Code Register (CCR) is more commonly known as the Processor Status Word (PSW) • Branch instructions check the status of the PSW • A branch is either taken or not taken. If it is taken, the branch address is loaded into the PC. Effectively, the sequential flow of instruction (or control) is interrupted.

17. E.g.1 Control System Bus Data Address Controller(System Clock) MDR (Data Buffer) MAR(Address Buffer) ID CCR Registers PC: 1003 InstructionRegister(IR) ALU Internal Bus

18. E.g.1 Control System Bus Data Address Controller(System Clock) MDR (Data Buffer) MAR1003 ID CCR Registers PC: 1007 InstructionRegister(IR) ALU Internal Bus

19. E.g.1 Control System Bus Data Address Controller(System Clock) MDR ADD AH, 2 MAR1003 ID CCR Registers PC: 1007 InstructionRegister(IR) ALU Internal Bus

20. E.g.1 Control System Bus Data Address Controller(System Clock) MDR ADD AH, 2 MAR1003 ID CCR Registers PC: 1007 IR:ADD AH, 2 ALU Internal Bus

21. E.g.1 Control System Bus Data Address Controller(System Clock) MDR ADD AH, 2 MAR1003 ID CCR: -ve Registers PC: 1007 IR:ADD AH, 2 ALU Internal Bus

22. E.g.1 Control System Bus Data Address Controller(System Clock) MDR ADD AH, 2 MAR1007 ID CCR: -ve Registers PC: 1009 IR:ADD AH, 2 ALU Internal Bus

23. E.g.1 Control System Bus Data Address Controller(System Clock) MDR:JL TARGET MAR1007 ID CCR: -ve Registers PC: 1009 IR:ADD AH, 2 ALU Internal Bus

24. E.g.1 Control System Bus Data Address Controller(System Clock) MDR:JL TARGET MAR1007 ID CCR: -ve Registers PC: 1009 IR:JR TARGET ALU Internal Bus

25. E.g.1 Control System Bus Data Address Controller(System Clock) MDR:JL TARGET MAR1007 ID CCR: -ve Registers PC: 1033 IR:JR TARGET ALU Internal Bus

26. E.g.2

27. E.g.2 Control System Bus Data Address Controller(System Clock) MDR MOV AH, SRC MAR1003 ID CCR Registers PC: 1007 InstructionRegister(IR) ALU Internal Bus

28. E.g.2 Control System Bus Data Address Controller(System Clock) MDR MOV AH, SRC MAR1003 ID CCR Registers PC: 1007 IR:MOV AH, SRC ALU Internal Bus

29. E.g.2 Control System Bus Data Address Controller(System Clock) MDR MOV AH, SRC MAR1063 ID CCR Registers PC: 1007 IR:MOV AH, SRC ALU Internal Bus

30. E.g.2 Control System Bus Data Address Controller(System Clock) MDR: 20 MAR1063 ID CCR Registers PC: 1007 IR:MOV AH, SRC ALU Internal Bus