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# Sep 3 rd , 2008 Majd F. Sakr msakr@qatar.cmu qatar.cmu/~msakr/15447-f08/

CS-447– Computer Architecture M,W 2:30 - 3:50pm Lecture 6 Instruction Set Architecture. Sep 3 rd , 2008 Majd F. Sakr msakr@qatar.cmu.edu www.qatar.cmu.edu/~msakr/15447-f08/. Hypothetical Machine. Consider the following hypothetical machine: Télécharger la présentation ## Sep 3 rd , 2008 Majd F. Sakr msakr@qatar.cmu qatar.cmu/~msakr/15447-f08/

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1. CS-447– Computer Architecture M,W 2:30 - 3:50pmLecture 6Instruction Set Architecture Sep 3rd, 2008 Majd F. Sakr msakr@qatar.cmu.edu www.qatar.cmu.edu/~msakr/15447-f08/

2. Hypothetical Machine Consider the following hypothetical machine: # registers = 16 {R0 to R15} require 4-bits to address them (24 = 16) # memory locations = 256 {M0 to M255} require 8-bits to address them (28 = 256)

3. Hypothetical Machine (cont’d) # instructions = 32 {Inst0 to Inst31} require 5-bits to be controlled (25 = 32) where Inst15 = Add (instruction # 15) & Inst9 = Load (instruction # 9)

4. Example 1: Add R0, R4, R11

5. The instruction In fact, each piece of an instruction can be considered as an individual number, & placing these numbers side by side forms the instruction.

6. Example 2: Load R13, 127

7. The instruction In fact, the instruction format Example: OpCode, Operand, Operand, Operandis fixed only for a specific operation

8. Note • When the OpCode consist of a memory R/W, the operand, Source Register 1 & 2 are combined to form the address field of the instruction. • When the OpCode consist of an immediate instruction, the operand, Source Register 1 & 2 are combined to form the constant whenever that is required.

9. The Instruction • OpCode: basic operation of the instruction • Destination Register: register where the result of the operations will be loaded • Source Register 1 & 2: registers where the data will be operated on

10. Instruction size = data word size As you can see from counting the number of bits, this hypothetical machine instruction takes exactly 17-bits which should be the same size as a data word.

11. x x x Design by Starting with the Instruction Size We would like to design a machine with: • Instruction size = 8 bits • Instruction number = 8 • No Operation • Add • Sub • Branch • Load • Store • Increment • Decrement 3-bits of the instruction word will be reserved to control the 8 desired instructions

12. Design by Starting with the Instruction Size So we are left with 5-bits for the operands, With which we can address at most: • 32 (= 25) memory locations • 32 (= 25) registers But if we chose to do so, we will be restricted in the number of operands in the instructions to one

13. x x x Design by Starting with the Instruction Size On the other hand if we wish to have instructions with 2 explicit operands; that is still possible with the 5-bits left. How ? ! ?

14. x x x How ? ! ? 3 4 5 6 7 Using bits 3 with 4 and bits 5 with 6 to address 4 registers.

15. Results • 8 Instructions • 2 operands addressing 4 registers with 2-bits each • 1 operand of 5-bits addressing 32 memory locations Note:# operands increases # registers decreases

16. Consider this Instruction Set

17. Execution of a simple program The following program was loaded in memory starting from memory location 0. 0000 Load R2, ML4 ; R2 = (ML4) = 5 = 1012 0001 Read R3, Input14 ; R3 = input device 14 = 7 0010 Sub R1, R3, R2 ; R1 = R3 – R2 = 7 – 5 = 2 0011 Store R1, ML5 ; store (R1) = 2 in ML5

18. The Program in Memory

19. Load R2, ML4 ; 010100110 R1 R3 I.R. 010100110 R2 000000101 ... P.C. 0 1 Load CPU

20. ReadR3, Input14 ; 100110100 010100110 100110100 R1 R3 000000111 R2 ... 000000101 1 2 Read CPU

21. SubR1, R3, R2 ; 000011110 100110101 000011110 R1 R3 000000010 000000111 R2 ... 000000101 2 3 000000101 000000111 Sub CPU

22. Store R1, ML5 ; 011010111 Next Instruction 011010111 R1 R3 Don’t Care 000000010 000000111 R2 ... 000000101 3 4 Store CPU

23. BeforeProgramExecution AfterProgramExecution In the Memory 000000010

24. Instruction Formats • Layout of bits in an instruction • Includes OpCode • Includes (implicit or explicit) operand(s) • Usually more than one instruction format in an instruction set

25. Instruction Length • Affected by and affects: • Memory size • Memory organization • Bus structure • CPU complexity • CPU speed • Trade off between powerful instruction types and saving space (bits).

26. Allocation of Bits • Number of addressing modes • Number of operands • Register versus memory • Number of registers • Address range • Address granularity

27. Addressing Modes • Immediate • Direct • Indirect • Register • Register Indirect • Displacement (Indexed) • Stack

28. Immediate Addressing • Operand is part of instruction • The address field points to the operand • e.g. ADD 525 • Add 525 to contents of accumulator • 525 is the operand • No memory reference to fetch data • Fast • Limited range

29. Immediate Addressing Diagram Instruction OpCode Operand Example: ADD 525 ; AC = AC + 525 In an Accumulator-Based machine, we would like to add 525 to the accumulator, the result will be stored in the accumulator itself.

31. Direct Addressing (cont’d) • Single memory reference to access data • No additional calculations to work out effective address • Limited address space

32. Direct Addressing Diagram Instruction Memory OpCode Operand Operand Example: ADD (Addr2) ; AC = AC + (2) ; (2) = 255

33. Indirect Addressing (1) • Memory cell pointed to by address field contains the address of (pointer to) the operand • EA = (A) • Look in A, find address (A) and look there for operand • e.g. ADD (A) • Add contents of cell pointed to by contents of A to accumulator

34. Indirect Addressing (2) • Large address space • 2n where n = address word length • May be nested, multilevel, cascaded • e.g. EA = ((A)) • Draw the diagram yourself • Multiple memory accesses to find operand • Hence slower

35. Indirect Addressing Diagram Instruction Memory OpCode Operand Pointer to Operand ADD ((1)); AC = AC + ((1)) ((1)) = (3) = 255 = operand Operand Memory

36. Register Addressing (1) • Operand is held in register named in address field • EA = R • Limited number of registers • Very small address field needed • Shorter instructions • Faster instruction fetch

37. Register Addressing (2) • No memory access • Very fast execution • Very limited address space • Multiple registers helps performance • Requires good assembly programming or compiler writing • C programming: • register int a;

38. Register Addressing Diagram Registers Instruction OpCode Operand Operand ADD R3 ; AC = AC + R3 ; AC = AC + 255

39. Register Indirect Addressing • Similar to indirect addressing • EA = (R) • Operand is in memory cell pointed to by contents of register R • Large address space (2n) • One fewer memory access than indirect addressing

40. Register Indirect Addressing Diagram Instruction Memory OpCode Operand Registers Operand Pointer to Operand Example:ADD (R3) ; AC = AC + (R3) = AC + (1) ; AC = AC + 255

41. Displacement Addressing • EA = A + (R) • Address field hold two values • A = base value • R = register that holds displacement • or vice versa

42. Displacement Addressing Diagram Instruction Memory OpCode Register R Address A Operand Registers Pointer to Operand + ADD (R2, BaseAddress) ; AC = AC + ; (R2+BaseAddress) ; AC = AC + (1) = AC + 255

43. Relative Addressing • A version of displacement addressing • R = Program counter, PC • EA = A + (PC) • i.e. get operand from A cells from current location pointed to by PC

44. Base-Register Addressing • A holds displacement • R holds pointer to base address • R may be explicit or implicit

45. Indexed Addressing • A = base • R = displacement • EA = A + R • Good for accessing arrays • EA = A + R • R++

46. Combinations • Postindex • EA = (A) + (R) • Preindex • EA = (A+(R)) • (Draw the diagrams)

47. Stack Addressing • Operand is (implicitly) on top of stack • e.g. • ADD Pop top two items from stack and add

48. 0 Byte 4 Byte 0 Byte 5 1 Byte 1 Byte 6 Byte 2 2 Byte 7 3 Byte 3 Byte ordering – Big Endian Bytes are ordered left to right (starting at “big end”) Byte 0 at the leftmost (most significant) to byte 3 at the rightmost (least significant) Word 0 Word 1 Bit 0 Bit 31

49. 3 Byte 7 Byte 3 2 Byte 6 Byte 2 Byte 5 Byte 1 1 Byte 4 0 Byte 0 Byte ordering – Little Endian • Byte 3 at the leftmost (MSB) to byte 0 at the rightmost (LSB) • Bytes are ordered right to left (starting at “little end”) Word 0 Word 1 Bit 0 Bit 31

50. An Example ISA – IA32

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