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Join this panel discussion on compiler optimization strategies featuring experts sharing insights on memory hierarchy, quality evaluation, performance prediction, and more. Learn about new ideas in compiler work with real impact on applications.
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Parallel Sessions: Compilers Moderator: Quinlan Panelists: MilindKulkarni (Purdue), David Padua (UIUC), P. Sadayappan (Ohio State), Armando Solar-Lezama (MIT), Olivier Tardieu (IBM), Nicolas Vasilache (Reservoir)
Panel Introductions Miland: • memory hierarchy / locality : highly demanded, even with Polyhedral David: • how to evaluate quality : compilers react differently to different codes • understand more about optimization problems : how to apply them. • predict the ultimate performance gain Saday: • landscape : architecture, data movement, up-bound analysis , irregular • apps, analyze apps • publication metrics: new ideas/prototypes vs. compiler work with • real impact on apps. Saman: need long term evaluation . Incentives to • attract researchers. JMC:finish compilers to deal with millions lines • of codes. Armando • Compiler fire and forget thing, all or nothing: too conservative → • force manual code transformation. solution: give control, give • feedback, support to users. Interactive compiler/refinement process
Panel Introductions Saman: reverse/rollback the process to check , need good UI people. • funding for UI/visualization Olivier • X10 language: ready to support CUDA using the place concept, future • work for NUMA Nicolas • confirm previous issues: issues, interaction with users. • new architecture challenges: parameterized code generation • Algorithms: correct representation for loop , communication, data • structure synthesis, how to put them together, apply combined • transformation.
Panel Questions Panel questions • * one rewrite/language: • high level specification like using Matlab • multiple, iterative, localized rewrites. • high level description for app features: locality, etc. • DSL , new general constructs like array loops, goto • * new/old compiler techniques: • array region/array section analysis → mulitithreaded, heterogeneous envionment. • Analysis : high level gap SSA • Interactive/feedback