Foundations of Software Design

1. Foundations of Software Design Lecture 3: How Computers WorkMarti Hearst Fall 2002

2. Today • Review/Revisit some things from last time • XOR and masking • What is inside a logic gate • Decoders • Circuits for addition / ALUs • Circuits for memory • Latches / Flip-Flops • DRAM (Dynamic Random Access Memory) • The CPU • It’s architecture • Interaction with machine code

3. XOR Revisited • TRUE only if just one of its inputs is TRUE • Another version of masking: • We can use it to show which object moved and where it moved from. Image from http://whatis.techtarget.com/definition/0,,sid9_gci213512,00.html#xor

4. XOR for Image Manipulation • First, threshold the images • All pixels are either 0 (black) or 1 (white) • Then, XOR the images together • Compare position (0,0) in first image to (0,0) in second • Compare position (10,3) in the first to (10,3) in the second • … • The truth table tells you what to do • White shows which item(s) moved, and to where Images from http://www.dai.ed.ac.uk/HIPR2/xor.htm

5. Results of the XOR • What does it mean for a pixel to end up black? • What does it mean for a pixel to end up white? • What has to happen to create a new white pixel? Called a bitwise operation Where have we seen this? Images from http://www.dai.ed.ac.uk/HIPR2/xor.htm

6. What is inside a logic gate? • Circuit for a logic switch • Open means logical 1 (connects output to power) • Closed means logical 0 (connects output to ground) Power supply Resistor Output signal Transistor Ground http://www.play-hookey.com/digital/experiments/logic_indicators.html

7. What is inside a logic gate? • Circuit for an LED indicator Power supply Resistors LED (diode) Input signal Transistor Ground http://www.play-hookey.com/digital/experiments/logic_indicators.html

8. What is inside a logic gate? • Good source online: • http://www.play-hookey.com/digital/experiments/ • http://www.play-hookey.com/semiconductors/

9. Circuit Board for Half-Adder http://www.seas.upenn.edu/~ee111/half-adder/Half-adder.html

10. n-bit Decoder:Takes as input n inputs; turns on 1 (and only 1) of outputs A B W X Y Z Notice where the invertors are. They look like the inputs of a truth table. Righthand image from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/Circuits/index.html

11. Circuits for Binary AdditionHalf Adder Images from http://www.play-hookey.com/digital/adder.html

12. Circuits for Binary AdditionFull Adder Images from http://www.play-hookey.com/digital/adder.html

13. Circuits for Binary AdditionFull Adder, 4 bit output + carry • Can link up an arbitrary number of input bits • Can modify this easily to do subtraction • Can also modify to do multiplication • How? • Usually division is done with a special floating point chip Images from http://www.play-hookey.com/digital/adder.html

14. Arithmetic Logic Unit (ALU)Add, Subtract, and Logic Operations http://www.seas.upenn.edu/~ee201/lab/LabALU/ALU.html

15. Circuit for using an ALU to control decimal LEDs http://www.seas.upenn.edu/~ee201/lab/LabALU/ALU.html

16. Flip-Flops • Also called a latch • Used to “remember” values • Keep the same value until the input signals a change • Example • Circuit with two inputs • Setting input A to 1 means “set output to 1” • Setting input B to 1 means “set output to 0” Input A output Input B

17. Simple Flip-Flop: The Problem • If both inputs change simultaneously, the final state of the latch cannot be determined ahead of time. This is called: • A Race Condition: the result depends on which input got changed first. • Nondeterministic: Not being able to predict what will happen with certainty. • Nondeterminism is very, verybad from the perspective of computer science (most of the time).

18. Clocked D Latch Solves the problem: Clock line allows the system to control when to read the inputs. BUT only allows for one input. Image from http://www.play-hookey.com/digital/

19. The clock • CPS (cycles per second): • The measure of how frequently an alternating current changes direction. • This term has been replaced by the term hertz (Hz). • gigahertz (GHz): • A unit of frequency denoting 109 Hz.

20. Memory • We represent data as 0’s and 1’s (bits) • 8 bits in a byte • 2 to 4 bytes in a word • Words represented schematically as rows in memory • Each word has • High order bit (most significant bit) • Low order bit (least significant bit) • We also represent locations as 0’s and 1’s • These locations are called addresses • Nice picture in the textbook

21. RAM(Random Access Memory) • One set of wires activates the appropriate location • Another set of wires • reads the data value from that location or • writes the data value to that location • RAM is arranged as a grid • Each column is a word (or some number of bytes) • First activate the correct column • Then either • Read the word’s values into the row output, or • Write the row’s values into the word • Read: get the value (don’t change it) • Write: set the value (change it)

22. How DRAM Works This example memory holds 8 bytes. Say we want to change the contents of memory address number 0101 (which is the fifth one from the right) First, activate the column that corresponds to this address Converting 0101 to 00010000 requires circuitry (not shown) Image adapted from http://www.howstuffworks.com/ram.htm

23. How DRAM Works Saw we want to set this memory addres to contain the value 01001011 When two activated lines cross, the cell at the intersection gets turned on. 0 1 0 0 1 0 1 1 Image adapted from http://www.howstuffworks.com/ram.htm

24. How DRAM Works Now we’ve set the value. Reading moves the data the other direction, onto the row (a special control wire, not shown, tells the circuit whether to read or write). Image adapted from http://www.howstuffworks.com/ram.htm

25. The CPU Images from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

26. Instructions and Their Representation How many instructions can this setup support? What is the largest memory address? 111111 = 1 + 2 + 4 + 8 + 16 + 32 = 63 1000000 = 64, so subtract 1 Images from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

27. Instructions and Their Representation Images from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

28. The CPU Bus: bundles of wires connecting things. Instruction Register: holds instructions. Program Counter: points to the current memory location of the executing program. Decoder: uses the 3-bit opcode to control the MUX and the ALU and the memory buses. MUX: multiplexer – chose 1 out of N ALU: adds, subtracts two numbers Accumulator: stores ALU’s output RAM: stores the code (instructions) and the data. Images from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

29. Machine code to add two numbers that are stored in memory (locations 13 and 14) and then store the result into memory (location 15). The Program Counter starts at memory location 0. Image adapted from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

30. The Program Counter starts at memory location 0. (Notice: the instructions and the data are both stored in the RAM.) This instruction moves along the bus into the instruction register. The decoder checks the number bit to see how to handle the opcode. Images from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

31. If the opcode number bit = 0, we want the operand to be used as a memory address. So the decoder switches the MUX to connect the operand to the RAM. If the bit were 1, the MUX would connect the operand to the ALU. The green wires do the addressing of the RAM. The blue wires do the reading to and writing from the RAM. Images from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

32. The Decoder tells the ALU this is a LOAD instruction. The memory location 13 is activated, and its value placed on the blue bus. This goes through the multiplexer into the ALU. It also trickles down into the Accumulator (Load is implemented as an ADD value to 0). The last step (always, except for a jump) is for the Program Counter to get incremented. Now it points to memory location 1. Images from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

33. Instruction: ADD 14 Similar to Load 13, except the ALU is given the ADD operation. The contents of the Accumulator becomes the lefthand operand, and the contents of memory becomes the righthand operand. Results of the AND end up in the Accumulator. The Program Counter increments. Images from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

34. Instruction: STORE 15 Memory address 15 is activated via the green bus. The contents of the Accumlator are written to RAM using the blue bus. The Program Counter increments. The next instruction is HALT. Images from http://courses.cs.vt.edu/~csonline/MachineArchitecture/Lessons/

35. CPU Performance • CPU cycles are not the whole story • The number of INSTRUCTIONS per second play a big role. • Each operation on the computer requires some instructions e.g., about 6 instructions required for the loop part of a simple for-loop. • Each instruction takes some number of cycles to execute. • So … a CPU with an instruction set and circuit design that requires fewer cycles to get operations done might have better performance than a CPU with a faster clock but more complicated circuitry.