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Efficient Power Management for Memory in Soft Real Time Systems

Efficient Power Management for Memory in Soft Real Time Systems. Midterm presentation. DRAM. Every Chip and rank in the DRAM has several powermodes:. Transition in and out of lower power modes needs time <-> read writes are only possible in active mode!. Power saving methods.

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Efficient Power Management for Memory in Soft Real Time Systems

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  1. Efficient Power Management for Memory in Soft Real Time Systems Midterm presentation

  2. DRAM Every Chip and rank in the DRAM has several powermodes: Transition in and out of lower power modes needs time <-> read writes are only possible in active mode!

  3. Power saving methods • Power aware scheduler • Power augmented History Scheduler • Throttling • Power dynamic transition • Power static transition

  4. Power saving methods • Power down unused chips (PD) • OS/Memory scheduler should use just minimal needed number of chips • Group read write accesses timely • Scheduler has to look at a stack of instructions and reorder them in a reasonable manner • Throttle speed/queue

  5. Power saving methods Processors/Caches Reads/Writes Read/Write instructions are queued in a stack Scheduler (AHB) decides which instruction is preferred Subsequently instructions are transferred into FIFO Memory Queue MEMORY CONTROLLER Read Write Queues Scheduler Memory Queue DRAM

  6. Chosen Approach • Many Power Down mechanism were evolved for DRAM, but usually they just handle two Power Modes • Use all 4 (active, standby, nap, power down) • Algorithm‘s primary concern is to meet timing constraints • If no negative influence is expected power down a chip/rank (according to simple algorithm): • Maybe allow fast „backdoor“ for highest priority tasks • Chips/Ranks where critical tasks are assigned to never power down and are served with FIFO manner • Throttle commands in Queue to allow better task execution time estimation, reordering mechanism and longer power down times

  7. A. Powering down unused chips Read/Write Queue Chip 3 C:1 - R:1 - B-1 - … K2 epochs later C:1 - …. - … PM K3 epochs later C:1 - … - … C:2 - … - … t Chip 2 C:1 - … - … C:2 - … - … - C:1 - … - … - C:2 - … - … -

  8. A. Reordering Read/Write Queue Chip 1 C:1 - R:1 - B-1 - … C:1 - …. - … C:1 - … - … C:2 - … - … Chip 2 C:1 - … - … C:2 - … - … - C:1 - … - … - C:2 - … - … -

  9. B. Guarantee Soft RT • Set Power Mode to result in a shorter estimated execution time then deadline • The Transfer function can be estimated by Manipulate PM Command threshold topt t Controller Transfer function + - If timing constraint is violated set a certain threshold for power down

  10. C. Power down used chips with gaps DRAM example with Matlab Pseudo code Control Algorithm: 1020 1020 1 1 5 1040 1040 2 2 0 1060 1060 3 3 0 1080 1080 4 4 0 63500 63500 5 5 0 156520 156520 6 6 0 337140 337140 7 7 0 656360 656360 8 8 0 1181980 1181980 1 8 0 2001000 2001000 2 8 0 Tasks 1- 10: (T,Dl,adr1,adr2, misses) 1 0 0 0 0 0 0 4 0 3 0 0 0 0 0 4 0 0 3 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 4

  11. D. Power down used chips with gaps • Tasks power down primary when timing constraints are hold but with reasonable power budget: tfastPM < topt < dl • Energy loop has only little influence • EL is mainly concerned with unused chips

  12. E. Throttling Approach • “Force memory commands to wait in the memory controller, DRAM structures can remain in low power mode for arbitrarily long periods of time, thereby modulating the DRAM’s average power consumption over some small time interval.” . . . active active stall stall T cycles T cycles 10,000 cycles 10,000 cycles time

  13. E. Key Difficulty: to determine accurate throttling • Inaccurate throttling • Power consumption is over the budget • Unnecessary performance loss App. 2 Application 1 A B

  14. E. Existing Method • By Ibrahim Hur and Calvin Lin • Model features that we determine • Power threshold • Number of Reads • Number of Writes • Bank conflict information • System model • Compute model coefficients during system design/installation by experiments with various memory access behavior.

  15. E. Throttling Mechanism with Feedback Control K*Δp(n) Throttling: y(n) Set Power Ps = 60W Write Rates Read Rates Controller RAM Ctrl RAM P(n-1) Monitor Power Calc

  16. E. Power Model Total Power: Detailed information refer to : http://www.micron.com/products/dram/syscalc.html And DRAMsim Manual at http://www.ece.umd.edu/DRAMsim/download/DRAMsimManual.pdf

  17. E. Simulator-DRAMsim+VisTool Device Utilization Utilization Statistic

  18. Outlook for future work • Feedback for change of threshold • Reordering Mechanism • “Backdoor” • Throttling Mechanism which doesn’t violate timing constraints • Simulations to show superior RT behavior of memory controller

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