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At90s2313. 8 bit microcontroller. Features. Utilize the AVR RICS architecture. AVR –high performance and low power RICS architecture 118 power full instruction mostly single clock cycle execution. 32*8 general purpose registers.

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  1. At90s2313 8 bit microcontroller

  2. Features • Utilize the AVR RICS architecture. • AVR –high performance and low power RICS architecture • 118 power full instruction mostly single clock cycle execution. • 32*8 general purpose registers. • 2K Bytes of in System Programmable Flash Endurance 1,000 write/erase cycle. • 128 BYTES of static RAM. • 128 BYTES of in System Programmable EEPROM. • 3 TIMMERS. • One 8 BIT Timer/Counter with separate Prescaler. • One 16 BIT Timer/counter with separate Prescaler. • Programming watchdog Timer with on chip oscillator. • On chip analog comparator. • Full duplex UART. • Low power idle and power down modes. • External and internal interrupt sources.

  3. Characteristic specification • Low power high speed CMOS technology. • Fully static operation. • Power consumption at 4MHZ 3v. • -active: 2.8mA. • Idle mode: .8mA • -power down mode:<1uA. • 15 programmable I/O lines. • Operating voltage. • -2.7V-6.0V. • 64 I/O Registers. • Three 16 bit special registers: • X , Y, Z Reristers.

  4. Block Diagram

  5. Addressing Modes • Program and data addressing modes: • Registers direct mode, single register Rd. • Register direct mode,two register Rd. • I/O addressing mode. • Data direct addressing. • Data indirect addressing. • Data indirect with Pre-Decrement. • Data indirect with Post-increment. • Relative program addressing.

  6. Special Registers • Status register. • Stack pointer. • General interrupt Mask register. • Timer/counter interrupt Mask register. • Timer/counter 0 control register. • Timer/counter control register A,B. • Watchdog Time control register. • EEPROM registers: • Address register, data register. control register. • Port B and D registers: • Data registers and data direction register. • UART registers.

  7. TIMRSMETimer/counter o • Timer/counter is either internally or externally clock. • The 8 BIT timer/counter can select clock source either from CK, or external pin. • It can be stopped by control register. • The overflow status flag is found in timer/counter interrupt flag register. • When timer 0 is externally clock, the external signal is synchronized with oscillator frequency of CPU. To assure proper sampling of clock, the minimum time between two external clock transition must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of CPU internal clock. • When it is use as even counter then output is connected to external pin.

  8. Timer/counter 1 • It is 16 BIT timer/counter. • It addition to all feature of 8 BIT it can also has ability of comparison and pulse-width modulator. • It support output compare function using the output compare register 1A-OCRIA as the data source to be compared to timer/counter 1 contents. The Output compare functions include optional clearing of the counter on compare matches. • It can also be provide 8,9,10 BITS PWM

  9. Watchdog Timer • The watchdog timer is clocker from a separate on chip oscillator, which run at 1MHZ. • By controlling watchdog prescaler, the watchdog reset interval is adjusted. • 8 different clock cycles periods can be selected to determined reset period.

  10. MemoryFlash memory • The aTI90S2313 contain 2K BYTES on chip in-system Programmable Flash memory for program storage. Since all are 32 or 16 BIT words, the flash is organized as 1K*16.The flash memory has an endurance of at least 1000 write/erase cycle. • As pc is 10 BIT wide, thus addressing the 1024 memory addresses.

  11. EEPROM • The AT90S2313 contains 128 BYTES of EEPROM data memory. • It is organized as a separate data space, in which BYTES can read and written. • It has an endurance of 10,000 write/erase cycles. • It used to registers control and address register. • Address register specifies the EEPROM address in the 128 BYTES EEPROM spac.The EEPROM data BYTES are addressed linearly between 0 and 127. • EEPROM data register contain the data to be written to the EEPROM in the address given by EEAR register. • EEPROM control register control transfer of data from or to EEPROM.

  12. UART • The AT90S2313 features a full duplex Universal asynchronous Receiver and Transmitter. The main features are: • Baud rate generator that can generate a large number of baud rates. • 8 or 9 BITS data. • Noise filtering. • Overrun detection. • Framing error detection. • False state bit detection. • Data transmission. • Data receiver.

  13. Ports • There are two ports in AT90S2313. • PORT B and PORT D. • Port b is 8 bit bi-directional I/O ports. Three I/O memory address locations are allocated for port B, one each for the data register-port B, data direction register DDRB, and the port B input pins-PINB.The port B input pins address is read only, while the data register and the data direction register are read/ write.All port pins have individually selectable pull-up resistors. • Port B has its own registers: • Control registers, data direction register. • All 8 pins in PORT B have equal functionality when use as digital i/o pins.

  14. Other function of port B • Port B can also be use as: • Clock input pin for memory up/done loading. bit 7 • Data output pin for memory up loading. bit6 • Data input pin for memory down loading. bit 5. • Output compare match output. bit 1.

  15. Port D • PORT d has 7 bi-directional I/Opins with internal pull up resistors. • Three i/o memory address location are allocated for the port D. data register port TD, Data direction register-DDRD, and the port D input pins-PIND. • Other function of port D: • Received data input for UART.PD0. • Transmit data output for the UART.PD1. • External interrupt 0 and 1 input.PD2 AND PD3. • Timer 0 and 1 external input. PD4 AND PD5.

  16. INTERRUPT • The AT90S2313 provide 10 different interrupt sources. • These interrupts and the separate reset vectors, each having a separate program vector in the program memory space. All the interrupt are assigned individual enable bits which must be set together with the I-bit in the status register in order to enable interrupt. • The lowest memory address is automatically assigned for reset.

  17. INTERRUPT TYPES • Reset and interrupts vectors: • RESET: Hardware pin, power on reset and watchdog reset. • INT0: External interrupt request 0. • INT1:External interrupt request 1. • TIMER1 CAPT1:Timer/counter 1 capture event. • TIMER 1 COMP1:Timer/counter compare match. • TIMER 1 OVF1: Timer/counter 1 overflow. • TIMER 0 OVF0:Timer/counter 0 overflow. • UART, RX:UART RX complete. • UART, UDRE: UART DATA register empty. • UART, TX: UART,TX complete. • ANA-COMP: Analog comparator.

  18. COMPARISON WITH 8051 • Both have 32 general purpose registers. • Both have 128B of RAM. • EEPROM is not available in 8051 but this has 128B EEPROM. • 8051 has two timers. it has three timers. • 8051 has 6 interrupt source. it has 10 interrupt source.

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