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Computer Organization CS224

Computer Organization CS224. Fall 2012 Lesson 29. Control Hazards. Branch determines flow of control Fetching next instruction depends on branch outcome Pipeline can’t always fetch correct instruction Still working on ID stage of branch In MIPS pipeline

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Computer Organization CS224

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  1. Computer OrganizationCS224 Fall 2012 Lesson 29

  2. Control Hazards • Branch determines flow of control • Fetching next instruction depends on branch outcome • Pipeline can’t always fetch correct instruction • Still working on ID stage of branch • In MIPS pipeline • Need to compare registers and compute target early in the pipeline • Add hardware to do it in ID stage

  3. Stall on Branch • Wait until branch outcome determined (in ID stage) before fetching next instruction

  4. Branch Prediction • Longer pipelines can’t readily determine branch outcome early • Stall penalty becomes unacceptable • Predict outcome of branch • Only stall if prediction is wrong • In MIPS pipeline • Can predict branches not taken • Fetch instruction after branch, with no delay

  5. MIPS with Predict Not Taken Prediction correct Prediction incorrect

  6. More-Realistic Branch Prediction • Static branch prediction • Based on typical branch behavior • Example: loop and if-statement branches • Backward branches: predict taken • Forward branches: predict not taken • Dynamic branch prediction • Hardware measures actual branch behavior • e.g., record recent history of each branch • Assume future behavior will continue the trend • When wrong, stall while re-fetching, and update history

  7. Pipeline Summary • Pipelining improves performance by increasing instruction throughput • Executes multiple instructions in parallel • Each instruction has the same latency • Subject to hazards • Structure, data, control • Instruction set design affects complexity of pipeline implementation The BIG Picture

  8. MIPS Pipelined Datapath §4.6 Pipelined Datapath and Control MEM Right-to-left flow leads to hazards WB

  9. Pipeline registers • Need registers between stages • To hold information produced in previous cycle

  10. Pipeline Operation • Cycle-by-cycle flow of instructions through the pipelined datapath • “Single-clock-cycle” pipeline diagram • Shows pipeline usage in a single cycle • Highlight resources used • “Multi-clock-cycle” diagram • Graph of operation over time • We’ll look at “single-clock-cycle” diagrams for load & store

  11. IF for Load, Store, …

  12. ID for Load, Store, …

  13. EX for Load

  14. MEM for Load

  15. WB for Load Wrongregisternumber

  16. Corrected Datapath for Load

  17. EX for Store

  18. MEM for Store

  19. WB for Store

  20. Multi-Cycle Pipeline Diagram • Form showing resource usage

  21. Multi-Cycle Pipeline Diagram • Traditional form

  22. Single-Cycle Pipeline Diagram • State of pipeline in a given cycle

  23. Pipelined Control (Simplified)

  24. Pipelined Control • Control signals derived from instruction • As in single-cycle implementation (see Fig 4.49) RegWrite Memto-Reg RegDst ALUop1 ALUop0 ALUsrc Branch MemRead MemWrite

  25. Pipelined Control

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