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Computer Organization and Architecture Module: The Nitty-gritty of Logic Gates to Processor Design

Computer Organization and Architecture Module: The Nitty-gritty of Logic Gates to Processor Design. Ashok Jhunjhunwala, ashok@tenet.res.in Apurva Jalit IIT Madras. The Nitty-gritty of Logic Gates to Processor Design: Module Outline. Lecture 1, 2 and 3: Design of an Execution Unit (EU)

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Computer Organization and Architecture Module: The Nitty-gritty of Logic Gates to Processor Design

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  1. Computer Organization and ArchitectureModule: The Nitty-gritty of Logic Gates to Processor Design Ashok Jhunjhunwala, ashok@tenet.res.in Apurva Jalit IIT Madras

  2. The Nitty-gritty of Logic Gates to Processor Design:Module Outline • Lecture 1, 2 and 3: Design of an Execution Unit (EU) • L1: DATA-FLOW • Interconnecting outputs of Basic Gates / flip-flops, tri-state connection, Bus, transfer of data output to Bus through ENABLE / READ • Connection of Bus to Gate Inputs and LATCH / WRITE; Single bit MOVE • Registers and Multi-bit DATA BUS • ADDRESS BUS to address and READ / WRITE individual registers; Memory, CONTROL Lines (Piano), multi-bit MOV Instruction

  3. Module Outline (cont) • L2: Arithmetic and Logic Unit (ALU) • Representing Numbers in the binary form and Arithmetic Operations (Refer Stallings, Course-pack Appendix) • Design of multi-bit Adders, Subtractors, AND, OR, EXOR, NOT, CMP other logic and arithmetic functions • Input Data Registers, Output Data registers, FLAG Register and Function Select • Interconnection ALU to Data Bus • Instructions: ADD, SUB, AND, CMP, NOT and CONTROL Lines (Piano) • L2: Shift Registers (SR) • Shift Register: ROTATE and Shift LEFT / RIGHT Instruction function, Data Bus Interconnect and CONTROL Lines (Piano)

  4. Module Outline (Cont) • L3: Advanced Functions • Address Indirect and use in MOV Instruction and CONTOL Lines • Load/ MOV Immediate and CONTROL Lines • L3: EU Summary: Registers / Memory, ALU, SR, DATA Bus, Address BUS, CONTROL Bus • L3: Using assembly language / Machine Language program to control processor through CONTROL BUS -- Piano Control • Lecture 4 & 5: Design of Control Unit and extension of Internal Bus for peripherals

  5. L1: Data Flow Design of an Execution Unit (EU)

  6. Processor Design • Processor Execution Unit (EU) • Data Flow • ALU and Shift-register • Advanced Functions • Controlling / Programming Execution Unit using Assembly / Machine Language • Processor Control Unit (CU) • Processor Interconnect to External Devices • Memory • Peripheral Control Unit

  7. LI DATA-FLOW Outline • 90% plus of all processor instructions consist of data flow • Basic Logic Gates / flip-flops • Interconnecting Gates, READ / Output Enable, WRITE / Latch • DATA Bus, Registers • ADDRESS Bus • Control Lines • MOV Instruction, causing data flow or data movement, keeps the processor moving irrespective of the program used • Arithmetic and Logic function (including Shift / Rotate) contributes to most of the other instruction • Together contributing to over 99% of all processor activities

  8. Data Flow components: Logic-gates & flip-flops and their Interconnects • Logic gatesand Flip-flops serve as the building blocks of any digital logic circuits • All basic operations like memory transfers, I/O or computer arithmetic are performed using logic gates and Flip-flops Flip Flop input output XOR AND NAND NOT OR Latch

  9. Interconnecting Gates / flip-flop outputs • What will happen if we connect Output of two Gates / flip-flops? They are likely to have short-circuit or burn Flip flop 1 0 1 1 The outputs can not be connected as they have different values, causing short circuit: likely to burn 1 0 0 0 1 1 AND NOT NOT

  10. Tristate Gates to the rescue • Tristate Gates : A gate with a switch at output • These gates have an additional input signal called output enable (OE) (also called READ as discussed later) • OE allows the output port to assume a additional state: high impedance that effectively disconnects the gate from the output (OUTPUT FLOATS) • This allows multiple gates to share the same output line or lines (such as a bus) NOT OE1 AND Tristate Gates with outputs connected (only one OE enabled at a time) OE2

  11. Flip Flops • A Flip flop is a sequential circuit that has two stable states and can be used to store state information • Flip flops are 1 bit memory holders that are equipped with data lines, an output enable and a read enable Flip flop Output data line (OP) Input data line(IP) WRITE (WR) or Latch READ / Output Enable (RD) Input data is latched (stored) in flip flop only when WR (Latch) is enabled. Similarly, Output line gives value stored in the flip flop only when RD (Output Enable) is enabled

  12. Single-bit Data Bus • When OUTPUT of multiple flip flops (single bit storage) is connected, a single bit Data Bus is created • Only one of flip flops on the bus can have its Output Enable ON at any point of time (others are OFF) • The bus has data corresponding to the stored value of Enabled flip flop • Output enable of a flip flop is also called READ (RD) as enabling it makes Data Bus read the flip flop data Flip Flop 2 Flip Flop 1 Flip Flop 3 IP IP IP OP OP OP Single Bit Data Bus RD RD RD

  13. Data Movement on Flip flop Output Data Bus Click on near each flip flop to read data from that flip flop onto the bus Data output Data output Data output READ READ READ F1 F2 F3 Data input Data input Data input Reset

  14. Now connecting the Data Bus to INPUTs of the flip flops • While RD of a flip flop will enable Data Bus to read the stored value of the flip flop • Latch (also called Write or WR as it enables Bus to write to FF) of a flip flop would write (store) the data on Data Bus to this flip flop • Thus pressing RD of flip flop 2 and WR of flip flop 1 will result into transfer of data from flip flop 2 to flip flop 1 • Two step task involving first flipflop 2 data to be read on the data bus and then written (stored) to flip flop 1 • MOV FF1-data -> FF2 Flip Flop 1 IP OP WR WR WR RD RD RD Flip Flop 2 IP OP Single Bit Data Bus Flip Flop 3 IP OP

  15. Moving Data between Flip Flops Using WR/RD input signals to make the data transfer possible Click first on Read from buttons to read data from flip flop onto the bus and then Write to Buttons to read the data loaded on the bus into the flip flop Read from F1 Read from F2 Read from F3 Data output Data output Data output READ READ READ F1 F2 F3 WRITE WRITE WRITE Data input Data input Data input Write to F1 Write to F2 Write to F3 Reset

  16. Representing Data bus as bi-directional BUS I/O lines Flip Flop 2 Flip Flop 3 Flip Flop 1 Flip Flop 1 Flip Flop 3 Flip Flop 2 IP IP IP OP OP OP WR WR WR WR WR WR RD RD RD RD RD RD I/O lines Single Bit Data Bus I/O lines

  17. Multibit Data Bus • Flip flops being single bit holders, form a single bit bus when connected to each other enabling single bit data transfer • What if we want multibit bus to move multiple bits of data in parallel? • We can connect flip flops in parallel planes to form a group of flip flops (together they hold a multi-bit word) • The data lines of the flip flops contained in the bus can be connected to form a multibit bus Flip Flop Group 1 Flip Flop 1 Flip Flop Group 1 Flip Flop Group 1 3-Bit Data Bus Single Bit Data Bus 2-Bit Data Bus 4-Bit Data Bus WR WR WR WR RD RD RD RD RD RD RD RD RD RD RD RD Flip Flop 2 Flip Flop Group 2 Flip Flop Group 2 Flip Flop Group 2 WR WR WR WR Flip Flop 3 Flip Flop Group 3 Flip Flop Group 3 Flip Flop Group 3 WR WR WR WR

  18. Flip Flops to Registers • The group of flip flops collectively form a multi bit data (also called data-word) holders: 8/16/32 bit memory are called Registers • To perform read and write operations from all the flip flops contained in the register, we have a common read enable and a write enable 4-bit Out Data Lines 8-bit Out Data Lines 8 bit Register 4 bit Register Register RD Register RD Register WR Register WR 8-bit Input Data Lines 4-bit Input Data Lines

  19. Multi-bit data bus enabling data transfer between Registers I/O lines Register R3 Register R2 Register R1 Flip Flop 1 Flip Flop Group 1 Flip Flop Group 1 Flip Flop Group 1 4 WR WR WR 4-Bit Data Bus WR WR WR WR RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD Flip Flop Group 2 Flip Flop 2 Flip Flop Group 2 Flip Flop Group 2 I/O lines 4-Bit Bit Data Bus WR WR WR WR I/O lines Flip Flop 3 Flip Flop Group 3 Flip Flop Group 3 Flip Flop Group 3 WR WR WR WR

  20. MOV Instruction • MOV: instruction in machine / assembly language for data transfer between Registers • an operation that forms 80-90% of the operations performed by the processor • MOV has to be supplied with 2 operands : one for destination and other for source MOV A, B where A is the source and B is the destination Sample Instruction and its expansion

  21. Memory and Data Bus m-bit Data Bus Memory • Set of registers together form a Memory • Each of the register in the memory is identified by an index i • Registers are named as R0, R1, R2, R3 …… R(n-1) • For every register: a WR line and a RD line • To enable data transfer each register connected to Data Bus and control the RD and WR lines of these registers to execute the desired transfer • Width of the data bus: maximum number of bits a Register can hold or needs to transfer m-bit n Registers 0..m-1 I/O lines WE0..n-1 lines RE0..n-1 lines Control Lines

  22. Piano Control n = 8 n = 4 n = 16 8bit Data Bus Memory • RD and WR Signals are the control signals that control the Data Movement • Consider these inputs similar to keys of a piano • As the number of registers increase, the keys of this piano increase • N Registers => 2N Keys • makes it very cumbersome to use 8-bit n Registers 0..7 I/O lines 16 Control Lines 8 Control Lines 32 Control Lines RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR Piano Control

  23. Using Decoder to Reduce the keys • Can decrease the number of these RD / WR keys by using decoder • Example: for 8 lines use a 3:8 decoder and 3 keys in place of 8 keys We can reduce the number of lines from 16 to 4 or from 32 to 5 or from 256 to 8 by using a decoder: in other words from n lines to log2(n) control 8 output Lines 3 Input Lines

  24. Address Bus • Similarly a specific Register out of n Registers forming a Memory can be selected using log2(n) address lines and an address decoder • Address lines together forming Address Bus • Now the function RD or WR for any register can be selected using a common RD and a common WR lines along with Address lines pointing to the register • Reduces the number of the control keys • Address lines of a Memory enable selection of individual Memory byte/word

  25. Using Address Bus with RD and WR lines • RD and WR lines: common CONTROL lines shared by all registers • A common read line: Enabling this line, puts the Data Bus in Read mode, but with data read from register selected by Address lines • A common write line: Use is similar to read line, except it writes the Data from Data Bus into the selected register • ANDed output of Read line and register select line (obtained from decoding address bus) enables RD of a particular register • Similarly, ANDed output of Write line and register select line (obtained from decoding address bus) enables WR of a particular register

  26. Either RD or WR operation at a time WR RD Data Bus Register RD RegisterSelect(from Address lines) WR Data Line

  27. To Sum Up: Memory, Data Bus, Address Bus & Control Bus m-bit Data Bus Memory m-bit n Registers 0..m-1 I/O lines RD WR Address Bus Control Lines/Bus

  28. L2: ALU and Shifter

  29. Reading Reference • Chapter 9: Computer Arithmetic, “Computer Organization and Architecture,” William Stallings, Pearsons (Eighth Edition) • Arithmetic and Logic Unit • Integer Representation • Integer Arithmetic • Floating Representation • Floating Point Arithmetic

  30. Arithmetic & Logic Unit (ALU) • Does the calculations • Everything else in the computer is there to service this unit • Handles integers • May handle floating point (real) numbers • Advanced Arithmetic functions can be carried out • Either by arithmetic routines / algorithms • Or a separate FPU (maths co-processor) Taken from http://www.ing.unlp.edu.ar/electrotecnia/arcom1/09_Arithmetic.pdf

  31. Design of multi-bit Adders and Subtractors • Combinatorial Logic can be used to design multi-bit parallel Adders and Subtractors • Two multi-bit input words can be ADDED or Subtracted giving an output word • Carry (CY) or Borrow (B) bits associated with adders and subtractors respectively: denoted here as FLAG bits • Similarly one can design multi-bit Logic functions, Comparators, Complement functions etc. Input 1 Input 1 A > B Adder Output Yes / No (Flag) Input 2 Input 2 Carry (CY)

  32. ALU: Collection of functional units with common inputs and outputs with Output enable (Fn Select) Input 1 Input 1 Input 1 Input 1 A > B XOR Adder Subtractor ALU Output Output Output Output Input 2 Input 2 Input 2 Input 2 Enable Enable Enable Enable All such units are present in the ALU

  33. ALU performs arithmetic and Logic operations on a set of registers • ALU encompasses many units • Each of this unit is responsible for performing one of the operations • Some of these circuits are adder, subtractor, comparator, XOR etc. • ALU Function Select lines enable one of these units to perform specific operation • Input from and output to a set of pre-defined registers on the bus • Flag register contain bits for CY, B, Comp result (Y/N), Zero etc. Adder Register C Subtractor Register A XOR Register B Flag Register Comparator Function Select Lines

  34. Function Select Lines • Each operation that an ALU can perform has a corresponding function line • Number of function lines = number of arithmetic /logic operations that a processor can perform • Each of these lines activate one of the functional units inside the ALU • processor designer decides which function line triggers which operation • Function lines activated/enabled by control unit of the processor

  35. Flag/Status Register • A flag register or Condition Code Register is a collection of status flag bits giving information about the state of last operation performed (result of) • Different bits in register acts as a separate status indicators (defined by processor designer) • Flag bits can be used as input in ALU operation (eg: Add with Carry) as well as input in an instruction (eg: Jump if Carry)

  36. Mapped Registers • Some processor registers mapped to serve a particular role for ALU • Mapped Input Registers: These are the input registers that are mapped to act as the Inputs to the ALU functional units • Mapped Output Register: Register that is used to always store the output of the ALU operation is called Mapped output register • Flag Register: Similarly, a register that is used by ALU to reflect the flag values generated after performing an operation is called flag register • These registers are hard wired to function as desired role • The processor designer assigns these roles to the register • Eg. R0, R1 -> Input registers, R2 -> Output register, R3 -> Flag Register

  37. Shift Register • While ALU performs additions / subtractions / logic functions, multiply and divide needs shift operations • Can be implemented using a shift register (flip-flops connected in series) • Processors have a Shifter • Input from and output to a specific register on the Data Bus • Function selected by Shift Right (SR) and Shift Left (SL) control signal • Specific Flags for incoming / outgoing shift bits • Rotate Left and Rotate Right signals use same Flag for incoming / outgoing Register A Fi Shifter Fj SL SR

  38. Control Lines for ALU and Shifter Arithmetic Logic Unit Data Registers Shift Register Flag Register Function Select Lines Shift/Rotate Control Lines We can use a decoder here too for the function control lines Status Lines / LEDs ControlLines / keys

  39. To Sum Up: ALU, SR, Control Bus with Memory, Address and Data Bus m-bit Data Bus Memory m-bit n Registers 0..(m-1) I/O lines Arithmetic Logic Unit 0..(m-1) I/O lines Shift Register Flag Register Piano Control Lines (keys & LEDs) Status Lines / LEDs Address Bus RD WR Control Lines

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