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High Performance Processors and Systems

High Performance Processors and Systems. Projects proposal for the HPPS course. Antonio Miele e-mail: miele@elet.polimi.it Office T.13 (ground floor, DEI building). Luca Fossati e-mail: fossati@elet.polimi.it homepage: www.elet.polimi.it/upload/fossati

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High Performance Processors and Systems

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  1. High Performance Processors and Systems Projects proposal for the HPPS course Antonio Miele e-mail: miele@elet.polimi.it Office T.13 (ground floor, DEI building) Luca Fossati e-mail: fossati@elet.polimi.it homepage: www.elet.polimi.it/upload/fossati Office N.154 (first floor, DEI building) Tel. 3459

  2. ReSP (Reflective Simulation Platform) • MultiProcessor simulation platform • Uses the SystemC and TLM libraries (high level hardware description languages based on C++) to describe the hardware components • Uses python to add reflective capabilities to C++ (unknown components can easily be connected together) Software ..................................... Xml arch. description Cache ARM ..... ReSP High Performance Processors and Systems BUS Memory Debugger Reliabilityissues Performancemeasures

  3. Projects • ReSP: • Development of new hardware modules using SystemC and TLM • Study of reliability issues on SystemC specifications • Performance characterization and studies • Extension of eSys with TLM capabilities High Performance Processors and Systems

  4. Processors • Description of new processor models (microblaze, nios ..) using ArchC (www.archc.org), an Architectural Description Language based on SystemC and TLM (2/3 students) • Study of the reliability issues on existing processor models (2/3 students) • Application on hardware and software fault detection techniques on both the processor and the application running on it • First attempt to fault injection simulations to test the achieved reliability level. High Performance Processors and Systems

  5. Other Components • Description of new bus models (AMBA AHB, OCP-IP...) and/or studies of reliability issues of the models (1/2 students) • Description of cache models: • Cache coherent models • Prefetching caches (use advanced techniques to load data before it is needed) • Ad hoc hardware components (mutual exclusion management, hardware scheduler) Processor Processor Memory ...... Cache Cache High Performance Processors and Systems BUS

  6. Other Reliability Studies Study of reliability of other SystemC descriptions High Performance Processors and Systems

  7. Performance characterization and estimation on different architectures Programs can have different performance figures when executed on different architectures In case more processors are performance prediction can greatly help choosing the right processor The project is: Execution of applications on ARM, PowerPC processors and on the mAgic Digital Signal Processor Extraction of performance figures Development of prediction models High Performance Processors and Systems

  8. eSys and TLM • eSys (http://www.esys-net.org/home.php): a SystemC implementation using the C# language • Reflection natively implemented in the language (no need to use C++ and python) • Almost as fast as native C++ • Still lacks TLM support • The project consists in the study of the SystemC TLM library and its translation in C# for the utilization with eSys High Performance Processors and Systems

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