1 / 9

Implementation of Variable-Block-Size Motion Estimation Algorithm Using Systolic Array Architecture

Implementation of Variable-Block-Size Motion Estimation Algorithm Using Systolic Array Architecture . Yen-Ting Lin Wei-Jen Chen. Outline. Motion estimation algorithms( Full Search Block Matching Algorithm) Systolic array architecture for motion estimation algorithms Implementations.

tyson
Télécharger la présentation

Implementation of Variable-Block-Size Motion Estimation Algorithm Using Systolic Array Architecture

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Implementation of Variable-Block-Size Motion Estimation Algorithm Using Systolic Array Architecture Yen-Ting Lin Wei-Jen Chen

  2. Outline • Motion estimation algorithms( Full Search Block Matching Algorithm) • Systolic array architecture for motion estimation algorithms • Implementations

  3. Fix-sized Full-Search BMA • Equation: • Disadvantage: Redundancy VS Accuracy • - Use small block size: • some blocks will have • identical MV, thus reduce • the efficiency of compression • Use large block size: • may mispredict the movement • of some small objects Reference frame (y) Current frame (x)

  4. Variable block size BMA • Split approach, usually in a quad-tree manner • The motion vector for the previous page can be represented as:

  5. Systolic array mapping for 4x4 full-search BMA [Yeo and Hu] • Write down the 6 level do loop algorithm • Reformatted into a three level nested do loops • Localize the indexes of the inner loop indexes • Project the 3-dim array two times into 1-dim systolic array

  6. Systolic array for variable block size ME (4x4 & 8x8) • Easy to implement • Short clock period • Large number of input pins Block of current frame 4 8 Block of reference frame

  7. Systolic array for variable block size ME (4x4, 8x8 &16x16)

  8. Implementation PE Data Flow System Schematic Diagram

  9. Implementation (cont’d) Implemented by Verilog; Verified by C/Matlab Waveform of 4x4 fixed size Waveform of 4x4 & 8x8 variable size

More Related