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Understanding Other Types of Gates in Combinational Logic

Explore the XOR, NAND, NOR gates and Universal Set's significance in combinational logic circuits. Learn how to implement various functions and applications of these gates. Study block diagrams, transformations, and more in this lecture.

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Understanding Other Types of Gates in Combinational Logic

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  1. CS 140 Lecture 6: Other Types of Gates Professor CK Cheng

  2. Combinational Logic: Other Types of Gates • Universal Set of Gates • Other Types of Gates • XOR • NAND / NOR • Block Diagram Transfers

  3. Universal Set Universal Set: A set of gates such that every switching function can be implemented with gates in this set. Ex: {AND, OR, NOT} {AND, NOT} {OR, NOT}

  4. Universal Set Universal Set: A set of gates such that every Boolean function can be implemented with gates in this set. Ex: {AND, OR, NOT} {AND, NOT} OR can be implemented with AND & NOT gates a+b = (a’b’)’ {OR, NOT} AND can be implemented with OR & NOT gates ab = (a’+b’)’ {AND, OR} This is not universal.

  5. {NAND, NOR} {NOR} {XOR, AND} X 1 = X*1’ + X’*1 = X’ if constant “1” is available. 1

  6. Other Types of Gates 1) XOR X Y = XY’ + X’Y XOR X Y • Commutative X Y = Y X • Associative (X Y) Z = X (Y Z) • 1 X = X’ 0 X = 0X’ + 0’X = X • X X = 0, X X’ = 1

  7. e) if ab = 0 then a b = a + b Proof: If ab = 0 then a = a (b+b’) = ab+ab’ = ab’ b = b (a + a’) = ba + ba’ = a’b a+b = ab’ + a’b = a b f) X XY’ X’Y (X + Y) X = ?? To answer, we apply Shannon’s Expansion.

  8. Shannon’s Expansion (for switching functions) Formula: f (x,Y) = x * f (1, Y) + x’ * f (0, Y) Proof by enumeration: If x = 1, f (x,Y) = f (1, Y) : 1*f (1, Y) + 1’*f(0,Y) = f (1, Y) If x = 0, f(x,Y) = f (0, Y) : 0*f (1, Y) + 0’*f(0,Y) = f(0, Y)

  9. Back to our problem… • X XY’ X’Y (X + Y) X = ? • X (XY’) (X’Y) (X + Y) X = f (X, Y) If X = 1, f (1, Y) = 1 Y’ 0 1 1 = Y If X = 0, f (0, Y) = 0 0 Y Y 0 = 0 Thus, f (X, Y) = XY

  10. 2) NAND, NOR gates NAND, NOR gates are not associative Let a | b = (ab)’ (a | b) | c = a | (b | c)

  11. 3) Block Diagram Transformation a) Reduce # of inputs.  

  12. b. DeMorgan’s Law  (a+b)’ = a’b’  (ab)’ = a’+b’

  13. c. Sum of Products (Using only NAND gates)   Sum of Products (Using only NOR gates)  

  14. d. Product of Sums (NOR gates only)  

  15. Part II. Sequential Networks Memory / Timesteps Clock Flip flops Specification Implementation

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