COMPUTER OPERATING PROPERLY MODULE (COP)

1. COMPUTER OPERATING PROPERLY MODULE (COP)

3. Module Objective • By the end of this module you should be able to: • Understand the COP timer function and purpose • Configure the COP for your application needs • Module exercise • Write a subroutine which will service the COP timer

4. IRQ LVI Direct Memory Access Module (DMA) System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) 68HC08 CPU RESET BREAK COP Internal Bus (IBUS) Random Access Memory (RAM) Serial Peripheral Interface (SPI) Electronically Programmable ROM Monitor ROM Serial Communications Interface (SCI) COMPUTER OPERATING PROPERLY (COP) MODULE • Watchdog timer system - free running Counter • Allows recovery from unexpected events • Runaway code • Software processing errors

5. COP Block Diagram SIM CGMXCLK SIM RESET CIRCUIT 13-BIT SIM COUNTER • COP Enable - Signal which inhibits COP counter • COPRRESET - Generated by SIM from accessing counter • IRST - Global Reset, resets COP counter SIM RESET STATUS REGISTER STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE COP MODULE COPEN (FROM SIM) 6-BIT COP COUNTER COPD (FROM MOR) RESET CLEAR COP COUNTER COPCTL WRITE

6. COP Functional Description • COP operation • Generates an asynchronous reset unless serviced • RST pin held low for 32 CGMXCLK cycles • COP bit in SIM SRS is set to 1 • Based on the COP 6 bit counter roll over • Input to the counter is CGMXCLK/8192 Hz • Counter can be disabled preventing COP time out • Requires servicing before timeout period • With 4.9152 MHz Crystal, COP timeout period is 53.3 ms

7. 8192 * 32 Seconds CGMXCLK frequency 8192 * 32 ~ 0.065536 seconds ~ 4000000 COP Reset Rate • Refresh rate depends on CGMXCLK frequency • COP must be serviced within: • Example: 4 MHz external crystal (CGMXCLK = 4 MHz) • COP needs to be serviced within 65.53ms

8. D7 D6 D5 D4 D3 D2 D1 D0 READ: Low byte of reset vector COPCTL $FFFF WRITE: Clear COP Counter RESET: UNAFFECTED BY RESET COP Control Register • COP Control register (COPCTL) • Overlaps the CPU reset vector • Writing any value to COPCTL before counter overflows: • Clears COP counter • Clears bits 12 through 4 of the SIM Counter • Prevents reset • Starts new timeout period • Reading COPCTL returns low byte of the reset vector

9. COP Exercise Write a routine to reset the COP timer.

10. Additional Information- Low Power Modes - • Low Power modes • WAIT • Operation continues during wait mode ( if enabled ) • To prevent a COP timeout you must periodically clear the COP counter • CPU service routine or DMA Service routine • STOP • Disables the clock(CGMXCLK) input to the COP module, Clears SIM counter • After exiting Stop, COP counter continues at last value

11. READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD MOR WRITE: RESET: UNAFFECTED BY RESET COP Enable/Disable • Mask Option Register (MOR) • COP Disable (COPD) • Controls COP module • EPROM/OTPROM byte 1 = COP module disabled 0 = COP module enabled (erased state) • NOTE: Mask Option Register contents cannot be changed by program • Bits set or cleared at time of EPROM/OTP programming

12. D7 D6 D5 D4 D3 D2 D1 D0 READ: Low byte of reset vector COPCTL $FFFF WRITE: Clear COP Counter RESET: UNAFFECTED BY RESET READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD MOR WRITE: RESET: UNAFFECTED BY RESET COP Register Summary

13. Exercise Solution • * COP Module ORG $7000RSTCOP LDA #$00 STA $FFFF ; Reset COP timer RTS