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Understanding Cache Behavior and Design: EE282h Programming Assignment #3 Overview

This document outlines the objectives and specifications for EE282h's Programming Assignment #3, focusing on cache behavior and design. Students will explore key issues in cache design and utilize a simulator to analyze the impact of various cache parameters on performance. The simulator, developed in 1997, simulates a dual-issue processor with specific cache settings and provides tools for performance optimization and cost analysis. Instructions for running the simulator and analyzing results are provided, along with guidelines for submission.

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Understanding Cache Behavior and Design: EE282h Programming Assignment #3 Overview

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  1. EE282h: Review Session #3 Programming Assignment #3: Cache Behavior and Design November 12th, 1998

  2. Overview • Project Objectives • Simulator Specifications • Running the Simulator • Analyzing the Results • Making improvements • Submission Guidelines

  3. Project Objectives • Introduce key issues in cache design • Provide tool for exploring the effect of different cache parameters on performance. • Illustrate how important memory systems are to modern processors.

  4. Simulator Specifications • Developed in 1997 and used in last fall’s EE282h. • Simulates a dual-issue processor. • 10ns clock cycle time (100MHz). • Only simulates the L1 Data Cache! • [write-back] • Event Driven Simulation. • Only file modify for the assignment: cachesim.c

  5. Initial Cache Specifications: • Cache Size: 4096 bytes • Line Size: 32 bytes • Associativity: 2-way • Write-Back • LRU replacement policy • No Victim Cache • No Write-Buffer

  6. How To Get the Simulator • Copy files from /usr/class/ee282h/p3 • benchmarks: source code and input files for compress95, tomcatv, vortex • cachesim: simulator source code • traces: execution traces for compress95, tomcatv, vortex. • cd to <your_directory>/p3/cachesim • make

  7. Cacheparms.txt [Abbrev] ############################################################################### # Sample parameters file # Note: Please adhere to the following format: # parm_name(space)=(space)value(return) # This format allows a simple parsing algorithm. ############################################################################### cache_bytes = 4096 line_bytes = 32 associativity = 2 hit_under_miss = 0 replace_policy = 0 have_victim = 0 have_Wbuffer = 0 array_ports = 1 write_policy = 0

  8. Running the Simulator • Modify cacheparms.txt to match the test to run. • cachesim <benchmark> • compress95 • tomcatv • vortex • May take 10-20 minutes or longer…..

  9. Analyzing your results • Optimize performance/cost • performance = 1/(CPI * 10.0ns) • cost is equal to $5000 divided by yield. • Each performance improvement incurs an area cost. Area effects the total yield of the wafer use and a larger area design will be a more expensive chip.

  10. Brief Synopsis of Yield Yield = Yield =

  11. Yield Continued…. • Exponential drop in yield as size decreases. • However total chips per wafer increases with size. • Cache simulator calculates yield and cost for you. • For more info: take EE382

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