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Advanced Design Techniques: Early Output Logic with Anti-Tokens at Manchester University

Explore the innovative concept of Early Output Logic with Anti-Tokens, an asynchronous logic approach developed by Charlie Brej and Jim Garside at the APT Group in Manchester University. This technique offers benefits such as reduced size, faster operation, and lower power consumption compared to traditional methods. Learn about the principles of anti-tokens, guarding, dual-rail latch, DIMS logic, and more. Discover how this cutting-edge technology enhances performance in asynchronous pipelines, tackles collisions, and eliminates timing hazards. Dive into the realm of dual-purpose signals, anti-token generation, and the practical applications of this groundbreaking logic design. Uncover the advantages of this approach over synchronous designs and embrace the future of fine-grain pipeline architectures.

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Advanced Design Techniques: Early Output Logic with Anti-Tokens at Manchester University

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  1. Early Output Logic with Anti-Tokens Charlie Brej, Jim Garside APT Group Manchester University Early Output Logic with Anti-Tokens

  2. Outline • Asynchronous Logic • DIMS (Delay Insensitive Minterm Synthesis) • Early Output Logic • Guarding • Anti-Tokens • Collisions • Conclusions Early Output Logic with Anti-Tokens

  3. Asynchronous Latch Ri Ro Latch Ai Ao Req Ack Early Output Logic with Anti-Tokens

  4. Asynchronous Pipeline Early Output Logic with Anti-Tokens

  5. Asynchronous Pipeline Stall Wait! Early Output Logic with Anti-Tokens

  6. Dual-Rail Latch • Dual-Rail • 00 = ‘NULL’ • 01 = 0 • 10 = 1 • 11 = Illegal • Return to ‘NULL’ Ri_0 Ro_0 Ri_1 Ro_1 Latch Ao Ai Early Output Logic with Anti-Tokens

  7. DIMS Logic C 0 C 0 C 1 C Early Output Logic with Anti-Tokens

  8. C C C C DIMS vs Early Output Logic Size:48 transistors Delay:4 inversions Size:12 transistors Delay:2 inversions Early Output Logic with Anti-Tokens

  9. Early Output Logic 0 0 1 Early Output Logic with Anti-Tokens

  10. Guarding Problem: • Inputs • Late • Unnecessary • Acknowledge before ready Solution: • Validity signal (Vo) Ri Ro Vo Latch Ao Ai Early Output Logic with Anti-Tokens

  11. Early Output Guarding 0 0 C 1 Early Output Logic with Anti-Tokens

  12. Anti-Tokens Don’t: • Stall entire stage until late input arrives Do: • Stall the latch instead • Early ‘Validity’ • Acknowledge before Data Early Output Logic with Anti-Tokens

  13. Anti-Token Generation 0 0 C A Early Output Logic with Anti-Tokens

  14. Anti-Token Propagation A A C A Early Output Logic with Anti-Tokens

  15. Token Pass T T T Early Output Logic with Anti-Tokens

  16. Anti-Token Pass A A A Early Output Logic with Anti-Tokens

  17. Token Anti-Token collision T T A Early Output Logic with Anti-Tokens

  18. Token Anti-Token collision 2 T ? A Early Output Logic with Anti-Tokens

  19. Dual-Purpose Signals • Arbiter free • Req: • Token Request • Anti-Token Acknowledge • Ack: • Anti-Token Request • Token Acknowledge Req Ack Early Output Logic with Anti-Tokens

  20. Conclusions • New, fine-grain, asynchronous pipeline • Faster than DIMS (2x) • Smaller than DIMS (4x) • Lower power than DIMS • Some speed advantages over synchronous designs • Counterflow - no arbitration • Requires some timing assumptions Early Output Logic with Anti-Tokens

  21. Timing Hazard example 0 A 0 C A Early Output Logic with Anti-Tokens

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