Enhancing Embedded Processors with Specific Instruction Set Extensions for Network Applications

1. Aristotle University of Thessaloniki Enhancing Embedded Processors with Specific Instruction Set Extensions for Network Applications A. Chormoviti, N. Vassiliadis, G. Theodoridis, S. Nikolaidis Section of Electronics and Computers, Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece nivas@physics.auth.gr

2. Outline • Motivation • Scope • Benchmarking Suite • Design Flow • Implementation • Experimental Results Aristotle University of Thessaloniki, IDAACS ‘05

3. Motivation • Great expansion of network applications • High performancedemands • Requirements for flexibility to support new protocols and future applications • Fast Time-to-Market requirements • While ASICs lack flexibility and GPP are prohibitively expensivein terms of energy-performance ASIPs exploits special characteristics of the application domain to meet the desired specifications Aristotle University of Thessaloniki, IDAACS ‘05

4. Scope • Design an ASIP for network applications based on low-cost enhancement of an existing processor • Follow a methodology for the implementation of the ASIP from a hardware-software perspective • Use the NetBench benchmarking suitefor network applicationsas a vehicle for representing the application domain Aristotle University of Thessaloniki, IDAACS ‘05

5. NetBench-benchmarking suite • A benchmarking suite for network applications which containing a large variety of tasks • Four kernels of the suite were used with a set of typical stimulus as inputs • CRC: CRC-32 checksum calculation • DRR: Deficit-roundrobin (DRR) scheduling • ROUTE: Tablelookupimplementation alongwithinternetchecksum • URL: URL-based switching Aristotle University of Thessaloniki, IDAACS ‘05

6. ASIP Design Flow • A RISC, MIPS-like machine is used as the base processor • The application is described in C/C++ • The instruction set is extended by special instructions in order to increase performance and reduce power consumption Aristotle University of Thessaloniki, IDAACS ‘05

7. ASIP Design Flow – Pruning • Network algorithm • Huge source code size • Only a small part of the code is responsible for power and time consumption • Pruning • Simulation, profiling, and analysis are performed • The crucial parts of the code are identified • Undesired parts of the code are hide Aristotle University of Thessaloniki, IDAACS ‘05

8. ASIP Design Flow – Assembly Generation • The GNU-GCC is used as the compiler • The compiler is cross-configured for the target architecture (MIPS) • The pruned code is used • Assembly code is generated Aristotle University of Thessaloniki, IDAACS ‘05

9. ASIP Design Flow – Analysis • The assembly code is analyzed with the GNU tools • Static analysis • The code is parsed • Basic Blocks are identified • Dynamic analysis • The code is simulated • Basic Blocks are weighted with execution frequencies • Frequently executed instructions are identified Aristotle University of Thessaloniki, IDAACS ‘05

10. ASIP Design Flow – Instruction Generation • Frequently executed instructions are consider • Instructions are reorder to form patterns • The ISA is extended with new complex instructions • Hardware modifications for the support of the new ISA are performed Aristotle University of Thessaloniki, IDAACS ‘05

11. ASIP Design Flow – Code Generation/Evaluation • Code generation • Identified patterns are substituted by the new defined instructions in the application assembly code • A hardware model (VHDL) is constructed and synthesized • Evaluation • Execution cycles • Clock speed • Power consumption Aristotle University of Thessaloniki, IDAACS ‘05

12. Instruction Set Extensions • 9 New instructions • 5 Control flow Instr. • 3 Addressing modes • 1 pure computation • Delay slot reduction mechanism • Cycle reduction up to 18.6 % Aristotle University of Thessaloniki, IDAACS ‘05

13. Hardware Modifications • Addition of a shifter for Shift+ALU operations • Enhancement of the Control Flow Unit with “Increment/Decrement and Branch” capability • Control logic to reduce the delay slots for Branch operations • New addressing modes combining addition/AND with Load/Store operations Slightly hardware overhead and no degradation of performance was introduced Aristotle University of Thessaloniki, IDAACS ‘05

14. Experimental Results • The ARM7TDMI and MIPS-like processors were consider for comparison with the designed ASIP • The hardware models of MIPS and ASIP were synthesized in STM 0.13um process • For the ARM7TDMI core information were taken from the datasheets Aristotle University of Thessaloniki, IDAACS ‘05

15. Performance Results • Cycle accurate simulations were performed • The ARMulator was used for the ARM core • The VHDL model was used for the MIPS and ASIP cores • Significant performance improvements are achieved • 80% avg. compared to ARM7 • 50% avg. compared to MIPS Aristotle University of Thessaloniki, IDAACS ‘05

16. Energy Results • Major source of energy consumption for embedded processors => instruction memory accesses • 0.13um SRAM Single port memories models were used • Significant energy reductions are achieved • 60% avg. compared to ARM7TDMI • 50% avg. compared to MIPS * Models obtained from Dolphin Integration Embedded Memory Generator Aristotle University of Thessaloniki, IDAACS ‘05

17. Conclusions • An ASIP for multimedia applications was designed following a simple design flow • The ASIP was designed with small enhancements of a popular processor • Experimental results prove that significant speedups and power savings can be achieved with these small enhancements • 50% avg. performance and energy consumption improvements compared to the base processor • Improvements come with small development cost Aristotle University of Thessaloniki, IDAACS ‘05

18. Thank You Questions??? Aristotle University of Thessaloniki, IDAACS ‘05