OCP functional verification : a language independent solution

1. OCP functional verification : a language independent solution DATE, Nice, April 2007

2. Yogitech Overview HQ/R&D in Europe (Italy) Founded in 2000 Strong business practices Strong Partnerships Verification Alliance Partner OpenChoice certified SPIRIT ARM OCP-IP Sponsor Member Active FVWG member Active SWG member Customers Most of the top 10 semiconductor companies Other technology leaders in the world top 50 ranking Verification IP Catalog On-chip interconnect protocol OCP 2.1 uVC Storage ATAPI 7.0 eVC Automotive CAN 2.0 A/B eVC LIN 2.0 eVC AMS Verification Kit Complete, integrated and automated verification flows for Incisive Built-in planning, management and verification execution features AMS Verification Kit™ Automate top- or block-level AMS designs GUI driven environment  no new language to learn Integrate analog and digital verification environments Increase quality & lower project risk YOGITECH Overview

3. yogitech and OCP-IP

4. OCP-based SoCs

5. Major challenges in verifying SoCs

6. Major challenges in verifying SoCs The verification know-how doesn’t reside in the language in which I implement the verification environment. But usually we have: different designs, different teams -> different language knowledge !! Specman ‘e’ ? System Verilog ? WHAT IF I DON’T HAVE TO CHOOSE?

7. OCP Universal Verification Component • Multi-language support Verification IP • SystemVerilog API • SystemC, ‘e’, and HDL environments supported • Best of both worlds • API for SystemVerilog environment creation & use model • Robust proven technology ‘e’ core: > 3,000 licenses worldwide • Proven methodology: uRM • Cadence Universal Reuse Methodology compliant • Based upon established eRM (Verisity)

8. OCP uVC Benefits • Increase verification productivity • Design verification set-up accelerated • Automated regression suite set-up and run • Reuse of components and tests • Increased verification quality • Automation of tests increases coverage space • Widely deployed and implemented technology • Leading edge support for advancing standard • Simplified verification management • Metric driven coverage for easy reporting

9. OCP 2.1 eVerification Component Database of ‘e’ Sequences Configuration parameters Configuration parameters Sequence driver Protocol Checker RAM BFM BFM Coverage OCP MONITOR OCP MASTER OCP SLAVE eRM compliant

10. OCP 2.1 uVerification Component Database of SV Sequences Database of ‘e’ Sequences SystemVerilog API SystemVerilog API SystemVerilog API Configuration parameters Configuration parameters Sequence driver Protocol Checker RAM BFM BFM Coverage Includes a plugin for IVB OCP MONITOR OCP MASTER OCP SLAVE uRM compliant Based on a robust and proven verification IP

11. OCP 2.1 uVC: Highlights

12. OCP 2.1 uVC: Highlights

13. uVC configuration: IVB plugin Graphical configuration using Incisive Verification Builder* *IVB is included in Specman 6.0

14. Module Level Verification /1 e/SV e/SV Bus monitor including Protocol checker Bus monitor including Protocol checker DUT OCP OCP MASTER AGENT SLAVE AGENT OCP uVC MASTER OCP uVCSLAVE e / SV Verification Environment

15. Bus monitor including Protocol checker Bus monitor including Protocol checker e/SV e/SV DUT OCP MASTER PORT STIMULUS GENERATOR OCP SLAVE PORT STIMULUS GENERATOR COLLECTOR OCP OCP Module Level Verification /2 e / SV VerificationEnvironment

16. OCP 2.1 uVC MASTER C TESTS CVL IP PCI DMA IP CPU OCP INTERCONNECT OCP 2.1 uVC MONITOR & CHECKER OCP 2.1 uVC MONITOR & CHECKER IP MEM CTRL DSP MEM IP OCP 2.1 uVC SLAVE e / SV Verification Environment System Level Verification

17. Roadmap

18. Conclusions

19. via Lenin 132/p 56017 San Martino Ulmiano Pisa (Italia) www.yogitech.com www.amsvkit.yogitech.com