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Lecture 3: Review CPU Design

Lecture 3: Review CPU Design. Alvin R. Lebeck CPS 220 Fall 2001. Administrivia. Read Chapter 3 Homework #1 Processor Design Control and Datapath Pipelining If you need to more information, please see Chapters 5 and 6 of Patterson & Hennessy, “Computer Organization & Design”.

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Lecture 3: Review CPU Design

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  1. Lecture 3: Review CPU Design Alvin R. Lebeck CPS 220 Fall 2001

  2. Administrivia • Read Chapter 3 • Homework #1 Processor Design • Control and Datapath • Pipelining • If you need to more information, please see Chapters 5 and 6 of Patterson & Hennessy, “Computer Organization & Design” CPS 220

  3. Basic ISA Classes Accumulator: 1 address add A acc ¬ acc + mem[A] 1+x address addx A acc ¬ acc + mem[A + x] Stack: 0 address add tos ¬ tos + next (JAVA VM) General Purpose Register: 2 address add A B A ¬ A + B 3 address add A B C A ¬ B + C Load/Store: 3 address add Ra Rb Rc Ra ¬ Rb + Rc load Ra Rb Ra ¬ mem[Rb] store Ra Rb mem[Rb] ¬ Ra CPS 220

  4. VAX-11 • Variable format, 2 and 3 address instruction • 32-bit word size, 16 GPR (four reserved) • Rich set of addressing modes (apply to any operand) • Rich set of operations • bit field, stack, call, case, loop, string, poly, system • Rich set of data types (B, W, L, Q, O, F, D, G, H) • Condition codes CPS 220

  5. Ri Rj v Kinds of Addressing Modes • Register direct Ri • Immediate (literal) v • Direct (absolute) M[v] • Register indirect M[Ri] • Base+Displacement M[Ri + v] • Base+Index M[Ri + Rj] • Scaled Index M[Ri + Rj*d + v] • Autoincrement M[Ri++] • Autodecrement M[Ri--] • Memory Indirect M[M[Ri]] memory reg. file CPS 220

  6. A "Typical" RISC • 32-bit fixed format instruction (3 formats) • 32 64-bit GPR (R0 contains zero) • 3-address, reg-reg arithmetic instruction • Single address mode for load/store: base + displacement • no indirection • Simple branch conditions • Delayed branch (sometimes) see: SPARC, MIPS, MC88100, AMD2900, i960, i860 PARisc, POWERPC, DEC Alpha, Clipper, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3 CPS 220

  7. Processor Input Control Memory Datapath Output The Big Picture • The Five Classic Components of a Computer • Today’s Topic: Datapath and Control Design CPS 220

  8. The Big Picture: The Performance Perspective • Performance of a machine was determined by: • Instruction count • Clock cycle time • Clock cycles per instruction • Processor design (datapath and control) will determine: • Clock cycle time • Clock cycles per instruction • In this lecture: • Single cycle processor: • Advantage: One clock cycle per instruction • Disadvantage: long cycle time • Multi cycle processor CPS 220

  9. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 immediate op rs rt 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits The MIPS Instruction Formats • All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type • Fields: • op: operation of the instruction • rs, rt, rd: the source and destination registers specifier • shamt: shift amount • funct: selects the variant of the operation in the “op” field • address / immediate: address offset or immediate value • target address: target address of the jump instruction CPS 220

  10. Clk PC Instruction Address Ideal Instruction Memory Instruction Rd Rs Rt Imm 5 5 5 16 A Data Address 32 Rw Ra Rb 32 Ideal Data Memory 32 DataOut 32 32-bit Registers ALU Data In B Clk Clk 32 An Abstract View of the Implementation CPS 220

  11. The Steps of Designing a Processor • Instruction Set Architecture => Register Transfer Language • Register Transfer Language => • Datapath components • Datapath interconnect • Datapath components => Control signals • Control signals => Control logic CPS 220

  12. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The ADD Instruction • add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address CPS 220

  13. CarryIn Select A 32 A 32 Sum Adder MUX Y 32 32 B B Carry 32 32 OP A 32 ALU Result 32 B Zero Combinational Logic Elements (Building Blocks) ADDER MUX ALU CPS 220

  14. Storage Element: Register (Building Block) • Register • Similar to the D Flip Flop except • N-bit input and output • Write Enable input • Write Enable: • negated (0): Data Out will not change • asserted (1): Data Out will become Data In Write Enable Data In Data Out N N Clk CPS 220

  15. RW RA RB Write Enable 5 5 5 busA busW 32 32 32-bit Registers 32 busB Clk 32 Storage Element: Register File • Register File consists of 32 registers: • Two 32-bit output busses: busA and busB • One 32-bit input bus: busW • Register is selected by: • RA selects the register to put on busA • RB selects the register to put on busB • RW selects the register to be writtenvia busW when Write Enable is 1 • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • RA or RB valid => busA or busB valid after “access time.” CPS 220

  16. Write Enable Address Data In DataOut 32 32 Clk Storage Element: Idealized Memory • Memory (idealized) • One input bus: Data In • One output bus: Data Out • Memory word is selected by: • Address selects the word to put on Data Out • Write Enable = 1: address selects the memoryword to be written via the Data In bus • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • Address valid => Data Out valid after “access time.” • Looks similar to register file. Why have registers? CPS 220

  17. PC Clk Next Address Logic Address Instruction Memory Overview of the Instruction Fetch Unit • The common RTL operations • Fetch the Instruction: mem[PC] • Update the program counter: • Sequential Code: PC <- PC + 4 • Branch and Jump: PC <- “something else” Instruction Word 32 CPS 220

  18. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Datapath for Register-Register Operations • R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt • Ra, Rb, and Rw comes from instruction’s rs, rt, and rd fields • ALUctr and RegWr: control logic after decoding the instruction Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result ALU 32 32 busB Clk 32 CPS 220

  19. Instruction<31:0> Branch Instruction Fetch Unit Jump Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr 5 5 5 MemtoReg busA Zero MemWr Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp A Single Cycle Datapath • We have everything except control signals (underline) CPS 220

  20. 1 Mux PC 0 0 Adder Mux 1 Adder Clk Instruction Fetch Unit at the Beginning of Add / Subtract • Fetch the instruction from Instruction memory: Instruction <- mem[PC] • This is the same for all instructions 30 Addr<31:2> 30 PC<31:28> Addr<1:0> “00” 4 Target Instruction Memory 30 Instruction<25:0> 26 30 32 30 “1” Jump = previous Instruction<31:0> 30 SignExt 30 imm16 16 Instruction<15:0> Branch = previous Zero = previous CPS 220

  21. 31 26 21 16 11 6 0 op rs rt rd shamt funct The Single Cycle Datapath during Add and Subtract • R[rd] <- R[rs] + / - R[rt] Instruction<31:0> Branch = 0 Instruction Fetch Unit Jump = 0 Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst = 1 1 0 Mux ALUctr = Add or Subtract Rt Rs Rd Imm16 Rs Rt RegWr = 1 5 5 5 MemtoReg = 0 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = 0 ExtOp = x CPS 220

  22. 1 Mux PC 0 0 Adder Mux 1 Adder Clk Instruction Fetch Unit at the End of Add and Subtract • PC <- PC + 4 • This is the same for all instructions except: Branch and Jump 30 Addr<31:2> 30 PC<31:28> Addr<1:0> “00” 4 Target Instruction Memory 30 Instruction<25:0> 26 30 32 30 “1” Jump = 0 Instruction<31:0> 30 SignExt 30 imm16 16 Instruction<15:0> Branch = 0 Zero = x CPS 220

  23. . . . . . . op<5> op<5> op<5> op<5> op<5> op<5> . . . . . . <0> <0> <0> <0> <0> op<0> R-type ori lw sw beq jump The “Truth Table” for RegWrite op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegWrite 1 1 1 0 0 0 • RegWrite = R-type + ori + lw • = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type) • + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori) • + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw) RegWrite CPS 220

  24. . . . . . . op<5> op<5> op<5> op<5> op<5> op<5> . . . . . . <0> <0> <0> <0> <0> op<0> R-type ori lw sw beq jump RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0> PLA Implementation of the Main Control CPS 220

  25. ALUop ALU Control ALUctr 3 RegDst func op 3 Main Control Instr<5:0> 6 ALUSrc 6 : Instr<31:26> Instruction<31:0> Branch Instruction Fetch Unit Jump <0:15> <21:25> <16:20> <11:15> Rd Rt Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr 5 5 5 MemtoReg busA Zero MemWr Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Extender Data Memory imm16 32 16 Instr<15:0> Clk ALUSrc ExtOp Putting it All Together: A Single Cycle Processor CPS 220

  26. Drawback of this Single Cycle Processor • Long cycle time: • Cycle time must be long enough for the load instruction: • PC’s Clock -to-Q + • Instruction Memory Access Time + • Register File Access Time + • ALU Delay (address calculation) + • Data Memory Access Time + • Register File Setup Time + • Clock Skew • Cycle time is much longer than needed for all other instructions CPS 220

  27. Overview of a Multiple Cycle Implementation • The root of the single cycle processor’s problems: • The cycle time has to be long enough for the slowest instruction • Solution: • Break the instruction into smaller steps • Execute each step (instead of the entire instruction) in 1 clock cycle • Cycle time: time it takes to execute the longest step • Try to make all the steps have similar length • This is the essence of the multiple cycle processor • The advantages of the multiple cycle processor: • Cycle time is much shorter • Different instructions take different number of cycles to complete • Load takes five cycles • Jump only takes three cycles • Allows a functional unit to be used more than once per instruction CPS 220

  28. The Five Steps of a Load Instruction Instr Decode / Reg Fetrch Instruction Fetch Address Data Memory Reg Wr Clk Clk-to-Q Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value ExtOp Old Value New Value ALUSrc Old Value New Value RegWr Old Value New Value Register File Access Time busA Old Value New Value Delay through Extender & Mux Register File Write Time busB Old Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busW Old Value New

  29. PCWr PCWrCond PCSrc BrWr Zero ALUSelA Target IorD MemWr IRWr RegDst RegWr 1 32 Mux 32 PC 0 0 Zero 32 Rs Mux Ra 0 32 RAdr 5 32 Rt Mux Rb busA 1 32 ALU Ideal Memory 32 Reg File 5 32 Instruction Reg 0 1 4 Rt 0 Rw 32 Mux WrAdr 32 1 32 Rd 32 Din Dout busW busB 32 1 2 32 ALU Control Mux 1 0 3 << 2 Imm Control Beq 6 Extend Op Rtype 16 32 ALUOp 6 Ori Func ExtOp MemtoReg ALUSelB Memory : Multiple Cycle Datapath

  30. Where to get more information? • Chapter 5 of CPS 104 text book: • David Patterson and John Hennessy, “Computer Organization & Design: The Hardware / Software Interface,” Morgan Kaufman Publishers, San Mateo, California, 1994. • For a reference on the MIPS architecture: • Gerry Kane, “MIPS RISC Architecture,” Prentice Hall. • Now: Pipelining CPS 220

  31. Introduction to Pipelining

  32. Overview • A Pipelined Processor : • Introduction to the concept of pipelined processor. • Pipelined Datapath • Pipeline example: Load Instruction • Reading: • Chapter 3 • OrChapters 5, 6 in the CPS104 text

  33. A B C D Pipelining: It’s Natural! • Laundry Example • Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold • Washer takes 30 minutes • Dryer takes 40 minutes • “Folder” takes 20 minutes • How long to do laundry?

  34. Sequential laundry takes 6 hours for 4 loads If they learned pipelining, how long would laundry take? 6 PM Midnight 7 8 9 11 10 Time 30 40 20 30 40 20 30 40 20 30 40 20 T a s k O r d e r A B C D Sequential Laundry

  35. Pipelined laundry takes 3.5 hours for 4 loads 6 PM Midnight 7 8 9 11 10 Time 30 40 40 40 40 20 T a s k O r d e r A B C D Pipelined Laundry: Start work ASAP

  36. 6 PM 7 8 9 Time 30 40 40 40 40 20 T a s k O r d e r A B C D Pipelining Lessons • Pipelining doesn’t help latency of single task, it helps throughput of entire workload • Pipeline rate limited by slowest pipeline stage • Multiple tasks operating simultaneously • Potential speedup = Number pipe stages • Unbalanced lengths of pipe stages reduces speedup • Time to “fill” pipeline and time to “drain” it reduces speedup

  37. Review: a Multiple-Cycle Implementation • The main single cycle processor’s problem: • The cycle time has to be long enough for the slowest instruction to complete execution. • Solution: • Break instruction execution into smaller steps • Execute each step in one cycle (instead of the entire instruction). • Short cycle time: time it takes to execute the longest step • Make all the steps have similar length • This is the essence of the multiple cycle processor • Multiple-cycle processor advantages: • Cycle time is much shorter • Different instructions take different number of cycles to complete • Load takes five cycles • Jump only takes three cycles • Allows a functional unit to be used more than once per instruction

  38. PCWr PCWrCond PCSrc BrWr Zero ALUSelA Target IorD MemWr IRWr RegDst RegWr 1 32 Mux 32 PC 0 0 Zero 32 Rs Mux Ra 0 32 RAdr 5 32 Rt Mux Rb busA 1 32 ALU Ideal Memory 32 Instruction Reg Reg File 5 32 0 1 4 Rt 0 Rw 32 Mux WrAdr 32 1 32 Rd 32 Din Dout busW busB 32 1 2 32 ALU Control Mux 1 0 3 << 2 Extend Imm 16 32 ALUOp ExtOp MemtoReg ALUSelB Multiple Cycle Processor • MCP: If a functional unit is used more than once per instruction -> cannot pipeline -> lower performance

  39. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Load Ifetch Reg/Dec Exec Mem WrB The Five Stages of a Load • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: Calculate the memory address • Mem: Read the data from the Data Memory • WrB: Write the data back to the register file

  40. Load Ifetch Reg/Dec Exec Mem WrB Key Ideas Behind Instruction Execution Pipelining • The load instruction has 5 stages: • Five independent functional units to work on each stage • Each functional unit is used only once! • A 2nd load can start doing Ifetch as soon as the 1st load finishes its Ifetch stage. • Each load still takes five cycles to complete. • latency is still 5 cycles • The throughput is much higher: • CPI is 1 with ~1/5th the cycle time. • Instructions start executing before previous instructions complete execution.

  41. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 1st lw Ifetch Reg/Dec Exec Mem WrB 2nd lw Ifetch Reg/Dec Exec Mem WrB 3rd lw Ifetch Reg/Dec Exec Mem WrB Pipelining the Load Instruction • The five independent pipeline stages are: • Read Next Instruction: The Ifetch stage. • Decode Instruction and fetch register values: The Reg/Decstage • Execute the operation: The Exec stage. • Access Data-Memory: The Mem stage. • Write Data to Destination Register: The WrB stage • One instruction enters the pipeline every cycle • One instruction comes out of the pipeline (completed) every cycle • The “Effective” Cycles per Instruction (CPI) is 1; ~1/5 cycle time Clock

  42. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Ifetch Reg/Dec Exec WrB The Four Stages of R-Type • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: ALU operates on the two register operands • WrB: Write the ALU output back to the register file R-type

  43. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock OOPS! We have a problem! R-type Ifetch Reg/Dec Exec Wr R-type Ifetch Reg/Dec Exec Wr Load Ifetch Reg/Dec Exec Mem Wr R-type Ifetch Reg/Dec Exec Wr R-type Ifetch Reg/Dec Exec Wr Pipelining the R-type and Load Instruction • We have a problem called a structural hazard or pipeline conflict: • Two instructions try to write to the register file at the same time!

  44. 1 2 3 4 5 Load Ifetch Reg/Dec Exec Mem WrB 1 2 3 4 R-type Ifetch Reg/Dec Exec WrB Important Observations • Each functional unit can only be used once per instruction. • Each functional unit must be used at the same stage for all instructions: • Load uses Register File’s Write Port during its 5th stage. • R-type uses Register File’s Write Port during its 4th stage. • How do we solve this pipeline hazard?

  45. 4 1 2 3 5 Mem R-type Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Mem WrB Ifetch Reg/Dec Exec Mem WrB Ifetch Reg/Dec Exec Mem WrB Ifetch Reg/Dec Exec Mem WrB Ifetch Reg/Dec Exec Mem WrB Solution: Delay R-type’s Write by One Cycle • Delay R-type’s register write by one cycle: • Now R-type instructions also use Reg File’s write port at Stage 5 • Mem stage is a NO-OPstage: nothing is being done. Effective CPI? Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R-type R-type Load R-type R-type

  46. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Store Ifetch Reg/Dec Exec Mem WrB The Four Stages of a Store • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: Calculate the memory address • Mem: Write the data into the Data Memory

  47. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Beq Ifetch Reg/Dec Exec Mem WrB The Four Stages of BEQ • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: ALU compares the two register operands • Adder calculates the branch target address • Mem: If the registers we compared in the Exec stage are the same, • Write the branch target address into the PC

  48. Clk Ifetch Reg/Dec Exec Mem WrB ExtOp ALUOp Branch RegWr 1 0 PC+4 PC+4 PC Imm16 PC+4 Imm16 Data Mem Rs Zero busA A Ra busB Exec Unit EX Unit RA Do Rb IF_Unit ID/Ex Register IF/ID Register Ex/Mem Register Mem/Wr Register 1 Rt WA RFile Mux Di Rw Di Rt 0 0 I Rd 1 ALUSrc RegDst MemWr MemtoReg A Pipelined Datapath

  49. You are here! Clk Ifetch Reg/Dec Exec Mem ExtOp ALUOp Branch RegWr 1 0 PC+4 PC+4 Imm16 PC+4 Imm16 PC = 12 Data Mem Rs Zero busA A Ra busB IF/ID: lw $1, 100 ($2) Exec Unit RA Do Rb IF_Unit Mem/Wr Register ID/Ex Register Ex/Mem Register 1 Rt WA RFile Mux Di Rw Di Rt 0 0 I Rd 1 ALUSrc RegDst MemtoReg The Instruction Fetch Stage • Location 8: lw $1, 0x100($2)$1 <- Mem[($2) + 0x100] MemWr

  50. You are here! Clk Ifetch Reg/Dec “4” PC+4 Adder 32 “8” PC = 12 Address lw $1, 100 ($2) Instruction Memory Instruction Detailed View of the Instruction Fetch Unit • Location 8: lw $1, 0x100($2)

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