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Sequential Optimization without State Space Exploration

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This work presents an innovative approach to optimize sequential circuits by identifying and eliminating redundancies without exploring the state space, which often leads to exponential complexity. The authors propose a method based on implications and recursive learning, which allows for safe delayed replacement of redundant components. The paper details definitions of various types of redundancies, showcases experimental results, and discusses future work in scaling this technique for larger circuits, making it a significant contribution to circuit optimization research.

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Sequential Optimization without State Space Exploration

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  1. Sequential Optimizationwithout State Space Exploration A. Mehrota, S. Qadeer, V. Singhal, R. Brayton, A. Sangiovanni-Vincentelli, A. Aziz Presented by: Andrew Mihal

  2. Outline • Goal • Definitions • Combinational Redundancies • Sequential Redundancies • Experimental Results • Future Work

  3. Main Idea • Optimize a sequential circuit for area • Locate and remove redundancies in the circuit • Avoid exploring state space (exponential) • Search for redundancies using a method based on implications and recursive learning • Result is a safe delayed replacement of original circuit • Scales well and works on large circuits

  4. Definitions • Redundancy: a net that does not affect circuit operation • Similar to an untestable stuck-at fault • Compatible redundancies: a set of redundant nets that are independent • Remove one redundancy and the other redundancies don't go away • Can simultaneously remove all redundancies

  5. Example • n1 = 0  n2 unobservable • n1 = 1  n2 = 1 • Therefore n2 is stuck-at-1 redundant • Can replace n2 with constant 1. • Similarly, n1 is stuck-at-1 redundant • But these redundancies are not compatible • Cannot be simultaneously replaced n1 n o n2

  6. Finding Combinational Redundancies • Choose a net • Assign it a value v and do implications. • Switch to v’ and do implications. • Find a commonality between the sets of implications. • Redundancy if: • A net n is constant b in both sets of implications • n is constant in one set and unobservable in the other

  7. Implication Rules b b’ 1 1 0 1 0 b’ b C1 C2 C3 0/1 1 1 0 1 0 1 0/1 C4 C5 C6

  8. Implication Rules •  means that a net is unobservable  0    O1 O2

  9. Recursive Learning • When no implication rules apply, recursively make another assumption • Helps to find more redundancies

  10. d f g c a e b Recursive Example • a = 0 0

  11. d f g c a e b Recursive Example 0 • a = 0  d = 0  0

  12. d f g c a e b Recursive Example 0 • a = 0  d = 0  f = 0 0 0

  13. d f g c a e b Recursive Example • a = 0  d = 0  f = 0 • a = 1  ? 1

  14. d f g c a e b Recursive Example 0 • a = 0  d = 0  f = 0 • a = 1  ? • d = 0  1

  15. d f g c a e b Recursive Example 0 • a = 0  d = 0  f = 0 • a = 1  ? • d = 0 f = 0 0 1

  16. d f g c a e b Recursive Example 1 • a = 0  d = 0  f = 0 • a = 1  ? • d = 0  f = 0 • d = 1  1

  17. d f g c a e b Recursive Example 1 • a = 0  d = 0  f = 0 • a = 1  ? • d = 0  f = 0 • d = 1  b = 1 1 1

  18. d f g c a e b Recursive Example 1 • a = 0  d = 0  f = 0 • a = 1  ? • d = 0  f = 0 • d = 1  b = 1  e = 1 1 1 1

  19. d f g c a e b Recursive Example 1  • a = 0  d = 0  f = 0 • a = 1  ? • d = 0  f = 0 • d = 1  b = 1  e = 1  f =  • f is stuck-at-0 redundant 1 1 1

  20. d f g c a e b Recursive Example • a = 0  f = 0 • a = 1  f is stuck-at-0 redundant •  f is stuck-at-0 redundant and can be replaced with constant 0

  21. Problem • This algorithm can find incompatible redundancies 1  0 1 1 1 0 0 1 

  22. Solution • Don’t let the algorithm overwrite an existing label b d a2 e a a1 c • a=0  c=1 • a=1  c=0, d=1  e=0 • No redundancies found

  23. Solution • We missed a redundancy! b d a2 e a a1 c • a=1  d=1 c=0  d=  a2=  • A2 is stuck-at-0 redundant

  24. Solution • It is safe to overwrite a constant label with a  • The authors prove it • But first, we need more definitions

  25. Definitions • Circuit • A graph G = (V, E) • V = PI’s, PO’s, gates, latches • E = wires • Assumption • A labeling of the nets P  E • Each net n  P is labeled with value v  {0,1}

  26. Definitions • AP • The set of all possible assumptions on P • Consistent • An assumption A  AP is consistent if there exists an assignment to the PI’s that satisfies it PI’s PO’s 1 0 Inconsistent assumption

  27. Definitions • Parent and Child nets • Share a common node v • Parent is an input to v • Child is an output of v • Sibling nets Parent v Child v Siblings

  28. Definitions • Implication graph • A DAG that details the implications leading from an assumption to a label a=1 Assumption b d a2 e c=0 a a1 c d= Label

  29. Definitions • Compatible labels • A set of labels C derived from an assumption A is compatible if: • Each label c  C has a valid implication graph Gc • Each label in Gc C • This means that no two implication graphs may have contradicting nodes

  30. Label Compatibility a1  a 0 0  a2 a=0 a1=0 a2= Incompatibility! a=0 a2=0 a1=

  31. Label Compatibility • One way to ensure compatible labels is to never switch a label • But this misses some redundancies, as we saw before • Now we will prove that it is safe to replace a constant label with a  label

  32. Proof by Contradiction • Assume that replacing a constant label by a  label creates an incompatibility Assumption New Implication Graph m = Incompatibility! ni Existing ImplicationGraph m = a

  33. Proof by Contradiction • Show that the existing implication graph can always be rewritten to not use m=a • 3 cases to consider: • ni-1 is a child of ni • ni-1 and ni are siblings • ni-1 is a parent of ni • These are the only implication relationships allowed given our implication rules ni-1 ni m = a

  34. Case 1: Child • We have two pieces of information • 1. ni-1 implies ni=a using some rule • 2. something implies ni= using some rule • No assignment satisfies both 1 and 2 • Thus, case 1 cannot happen ni=1 ni-1=1 ni= ni= ni-1=0 ni-1= 0

  35. Case 2: Sibling • 1. ni+1 is a sibling • Rewrite without using ni=a ni-1=a ni=a ni+1=a ni-1=a ni=a ni+1=a

  36. Case 2: Sibling • 2. ni+1 is a parent • Rewrite without using ni=a ni-1=a ni+1=a ni=a ni-1=a ni+1=a ni=a

  37. Case 2: Sibling • 3. ni+1 is a child • Rewrite without using ni=a ni= ni= ni+1=0 ni+1= 0 n’ ni= ni+1=0 0 n’

  38. Case 2: Sibling • What about this case? • If ni+1=, then ni+2, ni+3, … must also be  because a  can only imply a  ni= ni+1= ni-2=ci-2 ni-1=ci-1 ni=ci ni+1= ni+2=  Contains no  labels Can be modified not to use m=a

  39. Case 3: Parent • Same as case 2: sibling ni-1=a ni=a ni+1=a ni-1=a ni=a ni+1=a

  40. Case 3: Parent • Same as case 2: parent ni+1=a ni=a ni-1=a ni+1=a ni=a ni-1=a

  41. Case 3: Parent • Same as case 3: child ni= ni= ni+1=0 ni+1= 0 n’ ni= ni+1=0 0 n’

  42. Proof Summary • In every case, existing implication graph can be modified to be compatible with m= • Therefore no incompatibility arises when replacing m=a with m=, given a consistent initial assumption

  43. Original Algorithm for Optimization • Now we have formalized the way implications are found • Next, apply to sequential circuits • Choose a net • Assign it a value v and do implications. • Switch to v’ and do implications. • Find a commonality between the sets of implications. • Redundancy if: • A net n is constant b in both sets of implications • n is constant in one set and unobservable in the other

  44. Sequential Redundancies • Extend labeling algorithm to include time stamp with each label • New implication rule for latches: • Gate implication rules are the same • Implicator time stamps must be the same nt=a nt+1=a

  45. Sequential Redundancies • Time t is the time of the assumption • Implications can go forward across latches • t+1, t+2, ... • And backwards • t-1, t-2, ... • We can still overwrite a constant label with a  label • But we cannot overwrite a constant label with a different constant, even at a different time step

  46. C-delayed Replacement • A net may become stuck-at-n redundant at some time t+c • Removing the redundancy may change circuit behavior in the time between t and t+c • This is because latch outputs will initialize non-deterministically. • Assume no designated reset state • After time t+c the optimized circuit will behave the same as the unoptimized circuit

  47. C-delayed Replacement • This is allowed • The initial c period corresponds to a reset period, before the optimized circuit can be used • Most designers use lengthy resets anyway • In experimental results, c < 10000 • 10000 clocks = 100us at 100MHz • Not a severe restriction

  48. When to Remove a Sequential Redundancy • Replace net n with constant v if • nt’ = v • or nt’ is unobservable for all assumptions • For each assumption, there is an implication graph that shows nt’=v or nt’=

  49. When to Remove a Sequential Redundancy • Let t’’ be the least time offset on any label in those graphs • If t’’ > t’ then c = 0 • Else c = t’ - t’’ • n is c-cycle stuck-at-v redundant • Replace n with constant v to get ac-delayed safe replacement of the circuit

  50. Experimental Results • First run script.rugged on test circuit • Map to two-input gates and inverters • Run recursive learning redundancy removal algorithm • Compare optimized circuit area • CPU times from << 1 minute to 100 minutes on a dual Alpha 300 with 2GB RAM

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