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Analog Electronics Workshop Stability

Analog Electronics Workshop Stability. March 13, 2013. The Culprits. Capacitive Loads!. Cable/Shield Drive!. MOSFET Gate Drive!. Reference Buffers!. High Feedback Network Impedance!. High-Source Impedance or Low-Power Circuits!. Attenuators!. Transimpedance Amplifiers!.

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Analog Electronics Workshop Stability

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  1. Analog Electronics WorkshopStability March 13, 2013

  2. The Culprits Capacitive Loads! Cable/Shield Drive! MOSFET Gate Drive! Reference Buffers! High Feedback Network Impedance! High-Source Impedance or Low-Power Circuits! Attenuators! Transimpedance Amplifiers!

  3. Recognize Stability Issues • Oscilloscope - Transient Domain Analysis: • Oscillations or Ringing • Overshoots • Unstable DC Voltages • High Distortion

  4. Recognize Stability Issues • Gain / Phase Analyzer - Frequency Domain: Peaking, Unexpected Gains, Rapid Phase Shifts

  5. What causes amplifier stability issues?

  6. Fundamental Cause of Amplifier Stability Issues • Too much delay in the feedback network

  7. Quick Bode Plot Review

  8. Poles and Bode Plots • Pole Location = fP • Magnitude = -20dB/Decade Slope • Slope begins at fP and continues down as frequency increases • Actual Function = -3dB down @ fP • Phase= -45°/Decade Slope through fP • Decade Above fP Phase = -84.3° • Decade Below fP Phase = -5.7°

  9. Zeros and Bode Plots • Zero Location = fZ • Magnitude = +20dB/Decade Slope • Slope begins at fZ and continues up as frequency increases • Actual Function = +3dB up @ fZ • Phase = +45°/Decade Slope through fZ • Decade Above fZ Phase = +84.3° • Decade Below fZ Phase = 5.7°

  10. Op-Amp Loop Gain Model VOUT/VIN = Acl = Aol/(1+Aolβ) If Aol >> 1 then Acl ≈ 1/β Aol: Open Loop Gain β: Feedback Factor Acl: Closed Loop Gain

  11. Stability Criteria using 1/β & Aol At fcl: Loop Gain (Aolb) = 1 Rate-of-Closure @ fcl = (Aol slope – 1/β slope) *20dB/decade Rate-of-Closure @ fcl = STABLE **40dB/decade Rate-of-Closure@ fcl = UNSTABLE

  12. Stabilizing Unity Gain Buffer with Capacitive Load

  13. Unity Gain Buffer

  14. Capacitive Loads – Unity Gain Buffers - Theory

  15. Unity Gain Buffer Determine the issue: Pole in AOL!! ROC = 40dB/decade!! Phase Margin 0!! NG = 1V/V = 0dB

  16. Stability Options Unity-Gain circuits can only be stabilized by modifying the AOL load

  17. Method 1: Riso - Theory

  18. Method 1: Riso - Design Ensure Good Phase Margin: 1.) Find: fcl and f(AOL = 20dB) 2.) Set Riso to create AOL zero: Good: f(zero) = Fcl for PM ≈ 45 degrees. Better: f(zero) = F(AOL = 20dB) will yield slightly less than 90 degrees phase margin fcl = 222.74kHz f(AOL = 20dB) = 70.41kHz

  19. Method 1: Riso Theory: Adds a zero to the Loaded AOL response to cancel the pole

  20. Method 1: Riso When to use: Works well when DC accuracy is not important, or when loads are very light

  21. Method 1: Riso - Disadvantage Disadvantage: Voltage drop across Riso may not be acceptable

  22. Further Reading Presentation Article Series

  23. Stability Lab • Simulation • Measurement

  24. Ex 7.1: Hand Calculations 1. Simulate the open loop frequency response of the circuit below (answer given). Find the frequency that we should add the zero (70.37kHz). What is the phase margin?

  25. Ex 7.1: Hand Calculations 1. Use result from previous page to compute Riso (answer given): 1. Simulate open loop response (1/beta and Aol). Find the phase margin (83.6 deg).

  26. Ex 7.1: Simulation 1. Simulate the transient response with and without Riso. SW1 Closed SW1 Open

  27. Ex 7.1: Stability PCB Schematic Riso test circuit.

  28. Ex 7.1: Amplifier I/O PCB Setup Install OPA627 into socket U1

  29. Ex 7.1: Instrument Setup The instrument setup above will configure the signal source and scope for the circuit below so that we can see the I/O limitations.

  30. Ex 7.1: Expected Results (no Riso) Tina Results myDAQ Results

  31. Ex 7.2: Hand Calculations 1. The problem with this circuit is that Riso and RL form a voltage divider. With a 100mV input step, what output would you expect? Do hand calculation and use simulation with cursors to confirm the measurement. Note: the dual feedback-Riso circuit shown on the next page will solve the voltage divider issue.

  32. Ex 7.2: Stability PCB Schematic Solves the issue with drop on Riso.

  33. Ex 7.2: Instrument Setup Install OPA627 into socket U2

  34. Ex 7.2: Instrument Setup The instrument setup above will configure the signal source and scope for the circuit below so that we can see the I/O limitations.

  35. Ex 7.2: Expected Results Riso Riso+DF 1. The figure above show the results for both the Riso and the DF-Riso. Why is the the peak-to-peak output is different ?

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