ECEN4533 Data Communications Lecture #37 10 April 2013 Dr. George Scheets

1. ECEN4533 Data CommunicationsLecture #37 10 April 2013Dr. George Scheets Read 6.1 – 6.2 Problems: Web 27 & 28 Exam #2: < 15 April (DL) Corrected Quizzes due 10 April (Live) & 1 week after return (DL) Corrected tests due 17 April (Live) Design #2 Final Results Hi = 80, Low = 43.8, Ave = 68.60, σ = 14.23

2. ECEN4533 Data CommunicationsLecture #38 12 April 2013Dr. George Scheets Read 6.3 Problems: 4.2, 4.8, Web 29 Exam #2: < 15 April (DL) Corrected Quizzes due 1 week after return (DL) Corrected tests due 17 April (Live) Wireshark Project due by midnight 4 May (All) Late turn in NOT accepted 15 points + 20 points extra credit

3. 2013 OSU ECE Spring Banquet Sponsored in part by: • Hosted by Student Branch of IEEE • Wednesday, 17 April, at Meditations • Doors open at 5:30 pm, meal at 6:00 pm • Cash Bar • Sign up in ES202 to reserve your seat(s) • $5 a head (for a $16 meal!) • if pay in advance and resume submittedto OSUIEEEresume@gmail.com< noon, 16 April. Otherwise $8. • Speaker: Dr. Matt PerryDirector, SiArch • Dress is Business Casual • Many door prizes available!+10 points extra credit • All are invited!

4. Ways to decrease P(Bit Error) • Crank up power out • Reduce noise in system • Slow down transmitted bit rate • Use directional antennas • Need some fancy DSP to steer beams • Use Forward Error Correcting codes • Add controlled redundancy to bit stream • Extra parity bits must be transmitted • System at BW limit w/o FEC? Go M-Ary or reduce Layer 2-7 bps

5. No coding: Binary System Source Channel Coder • Source: Outputs a bit stream • Channel Coder: Maps bit stream into a form suitable for channel • Channel: Attenuates, distorts, & adds noise • Symbol Detector: Looks at received symbol and decides (if binary) "1?" or "0?" Suppose P(Bit Error) = 0.1 Symbol Detector Channel

6. 2:1 FEC Binary System 2R coded bps Source Coder: Input = 1 bit. Output = Input + Parity bit. Source Channel Coder • Suppose P(Coded BE) = 0.1 • P(Layer 2-7 BE) also = 0.1 R bps Layer 2-7 *Binary → 2x BW *4-Ary → same BW 2 bits/symbol R bps 2R coded bps Source Decoder: Looks at blocks of 2 bits. Outputs 1 bit. Symbol Detector Channel

7. Example) Two bit code words • Suppose you now transmit each bit twice, and P(Code Bit Error) = .1 • Legal Transmitted code words; 00, 11 • Possible received code words00, 11 (appears legal, 0 or 2 bits decoded in error) 01, 10 (clearly illegal, 1 bit decoded in error)P(No bits in error) = .9*.9 = .81P(One bit in error) = 2*.9*.1 = .18P(Both bits in error) = .1*.1 = .01 • Decoder takes 2 Code bits at a time & outputs 1 bit of DataIf illegal code word received, it can guess 0 or 1.81% + 18%(1/2) = 90% of time the correct bit is output 1% + 18%(1/2) = 10% of time the incorrect bit is output • Same performance as No Coding @ twice the bit rate

8. 3:1 FEC Binary System 3R coded bps Source Coder: Input = 1 bit. Output = Input + 2 Parity bits Source Channel Coder • Suppose P(Code BE) = 0.1 R bps Layer 2-7 *Binary → 3x BW *8-Ary → same BW 3 bits/symbol R bps 3R coded bps Source Decoder: Looks at blocks of 3 bits. Outputs 1 bit. Symbol Detector Channel

9. Example) SSD 3 bit code words • Transmit each bit thrice, P(Code Bit Error) = .1 • Legal Transmitted code words; 000, 111 • Possible received code words000, 111 (appears legal, 0 or 3 bits in error) 001, 010, 100 (clearly illegal, 1 or 2 bits in error)011, 101, 110 (clearly illegal, 1 or 2 bits in error)P(No bits in error) = .9*.9*.9 = .729P(One bit in error) = 3*.92*.1 = .243P(Two bits in error) = 3*.9*.12 = .027P(Three bits in error) = .1*.1*.1 = .001 • Decoder takes 3 bits at a time & outputs 1 bit. Majority Rules.72.9% + 24.3% = 97.2% of time correct bit is output .1% + 2.7% = 2.8% of time incorrect bit is output • Improved performance as No Coding @ thrice the bit rate

10. Local Oscillator On Frequency & Phase Cos(0) X =

11. Local Oscillator off frequency Cos(2πΔf) X =

12. Doppler Effect 60 mph (26.8 m/sec), 2 m offset

13. Receiver Phase Locked Loop LPF with negative gain. cosωct (from antenna) Active Low Pass Filter X 2 sinα cosβ = sin(α-β) + sin(α+β) Voltage Controlled Oscillator -sin((ωvco -ωc)t+θ) sin((ωvcot +θ) VCO set to free run at ≈ ωc VCO output frequency = ωc + K * input voltage

14. Phase Locked Loop LPF with negative gain. cosωct (from antenna) Active Low Pass Filter X Voltage Controlled Oscillator -sin((ωvco -ωc)t) sin(ωvcot) VCO frequency and phase locked. ωvco-ωc = 0 & θ = 0 Input to VCO = 0 volts.

15. Phase Locked Loop LPF with negative gain. cosωct (from antenna) Active Low Pass Filter X Voltage Controlled Oscillator sin((ωvcot )+θ) -sinθ VCO on frequency & positive θ? VCO phase is slightly ahead & needs to slow down. Negative voltage momentarily applied.

16. Phase Locked Loop LPF with negative gain. cosωct (from antenna) Active Low Pass Filter X Voltage Controlled Oscillator -sin(ωvco -ωc)t sinωvcot VCO off frequency? Oscillating input voltage moves VCO frequency up & down. If close enough to input, system will lock.

17. M-Ary Signaling • One of M possible signals transmitted each symbol interval • Tends to be used where bandwidth is tight & SNR decent at the receiver. • Each symbol can represent log2(M) bits • Example: In 16 PSK • one of 16 possible phase angles is transmitted every symbol interval • each symbol can represent 4 bits • QAM normally used • each symbol has different amplitude & phase