Sleep Transistor Circuits for Fine-Grained Power Switch-Off with Short Power-Down Times

1. Sleep Transistor Circuits for Fine-Grained Power Switch-Off with Short Power-Down Times Mohammad Hashem Haghbayan Technical Faculty of Tehran University VLSI Seminar Dr.Fakhraie St. Henzler1, Th. Nirschl1,2, S. Skiathitis1,3, J. Berthold2, J. Fischer1, Ph. Teichmann1, F. Bauer1, G. Georgakos2, D. Schmitt-Landsiedel1 1 Technical University Munich, Munich, Germany 2 Infineon Technologies, Munich, Germany 3 now with IBM, Böblingen, Germany

2. Outline • Concept of fine-grained sleep transistor scheme • 16 bit Multiply-Accumulate-Unit as demonstrator • Measurement methodology & techniques for minimum power-down time reduction • Fractional switch activation for slow operation mode • Double switch scheme for fast block activation • Conclusion

3. Footer and Header fine-grain sleep transistorimplementation in NAND gate [1]

4. Coarse-Grain Sleep Transistors[1]

5. Grid style sleep transistor implementations[1]

6. Ring style sleep transistor implementations[1]

7. Concept of Fine-Grained Power Switch-Off • SOC with large blocks • individual activity profile • varying frequency requirements • Block level MTCMOS • Fine-grained MTCMOS • small sub-blocks • short power-down times SOC DSP technology scalingincreases leakage ApplicationProcessor

8. 16 bit MAC System Overview • 16 bit MAC as representative SOC building block • Two stage pipeline • booth(2) precoding stage • Han Carlson adder stage • High threshold PMOS sleep transistor (3 x 128 x 1.5m) • Input / output cache and BIST for full speed testing • Standard-cell based design using multi-Vth option • 130nm low-power CMOS technology

9. Multiply-Accumulate-Unit[2]

10. Measurement of Max. Frequency[2] 5 % speed degradation and 8.5 % area overhead 9.5 % speed degradation and 2.8 % area overhead

11. Leakage Reduction[2] Super cut-off (SC):dramatically reduced leakage for appropriateunderdrive valuesachievable GIDL 85 °C

12. Frequency vs. Leakage Features[2]

13. Leakage Reduction & Overhead[2] what is the minimumpower-down time?

14. Minimum Power-Down Time[2] Proposed measurement setup for experimental determination of minimum power-down time

15. Temperature & Supply Voltage Dependence[2] crossover • leakage currents ( e.g. temperature, VDD, Vth ) • minimum power-down time  • convergence time 

16. Switching Overhead[2] turn off turn on

17. Charge Recycling Scheme[2] turn off turn on

18. Efficiency of Charge Recycling[2]

19. Impact of Virtual Supply Reduction[2] • Further reduction of minimum power-down time by fractional switch activation in slow mode of operation • Also observed: reduction of dynamic power 1.2V, 25 °C

20. fast medium slow t VDD Power Impact of Adaptive Supply[2] • Quadratic impact on dynamic power consumption: • Reasonable overhead only for large logic blocks

21. Virtual Supply Reduction[2] • Reduced switching power min. power-down time  • Linear impact on dynamic power consumption: • Lower power saving but negligible overhead VDD fast medium slow t

22. Power-Up Process • Current spikes during block activation can causetiming violations in surrounding blocks • Two contributors: • Recharging of internal circuit nodes • Uncontrolled transient glitching activity • Double switch scheme suppresses glitching • Activate gates in two phases • Demonstrated for filter circuit with NMOS sleep transistors in 90nm low-power CMOS

23. Double Switch Scheme[2]

24. Impact of Double Switch Scheme[2] Measured results for filter circuit with NMOS sleep transistors

25. Conclusion[2] • 130nm CMOS 16-bit mixed Vth pipelined MAC • PMOS sleep transistor results in up to 5500 x leakage reduction with only 8.5% area overhead and 5% frequency reduction • Accurate measurement methodology for minimum power-down time characterization • Charge recycling & fractional switch activation for reduction of minimum power-down time • Double switch scheme for reduction of current spikes during block activation

27. References 1- Sleep transistor design and implementation – simple concept yet challenges to be optimum Kaijian Shi, David Howard 2- sleep transistor circuits for fine-grained power switch-off with short power down times St. Henzler1, Th. Nirschl1,2, S. Skiathitis1,3, J. Berthold2, J. Fischer1, Ph. Teichmann1, F. Bauer1, G. Georgakos2, D. Schmitt-Landsiedel1