1. Lucas-Lehmer Primality TesterPresentation 6March 1st 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: Modular Arithmetic unit with a creative use This is my presentation, there are others like it but this one is mine

2. Status • Finished • Project Chosen • C simulations • Behavioral Verilog • Structural Verilog • Revised Floor Plan • Schematics • Pathmill Simulation of Top Level • In Progress • Layout • Layout Simulations • To Do • More Layout • Layout Simulations

3. Transistor Counts

4. Power Consumption

5. Sub_16

6. Sub_16 Simulation X = 32 Y = 7 OUT = 25

7. Top Simulation S1 = (4 * 4 - 2) mod 127 = 14

8. Top Simulation S2 = (14 * 14 - 2) mod 127 = 67

9. Pathmill Results • Shift_Left = .610 ns • Shift_Right = .610 ns • Mod_P = .610 ns • Mod_Add = 8.993 ns • Partial_Products = 5.135 ns • Longest Path from Top Simulation = 12.703ns

10. Block Area Estimates (Updated)

11. Updated Floorplan

12. What’s Next • Continue Layout • Simulate Layout • Power Estimations for Layout

13. Questions?