Computer-Aided Verification of Electronic Circuits and Systems

Computer-Aided Verification of Electronic Circuits and Systems EE219A – Fall 2002 Professor: Prof. Alberto Sangiovanni-Vincentelli Instructor: Alessandra Nardi

Administration • Office Hours: Th: 11.30-13.00 in 545H • Course mailing list: send e-mail to nardi@eecs.berkeley.edu • Course website: http://www-cad.eecs.berkeley.edu/~nardi/EE219A

Grading • Grading will be assigned on: • Project ( 50% ) • Homework ( 20% ) • Midterm ( 30% ) • There will be approximately 5 bi-weekly homework and a take-home midterm • No final

Projects • Groups of 2 people are strongly recommended • Tentative schedule: • Make your choice by October 21 • First update: October 31 • Second update: November 21 • Final presentation: December 3 and 5 • May be shared with other classes you are taking

Major Verification Tasks Design Concept Is what I asked for what I want? Design Verification Design Description Is what I asked for what I got? Synthesis Implementation Verification Design Implementation

Functional Verification • Specification Validation: Are the specifications consistent? Are they complete, i.e. if the design satisfies them are we sure that it is correct? • Design Verification: Is the “entry” level description of my design correct? Most common reason for chip failure. • Implementation Verification: Are the different levels of abstractions generated by the design process equivalent?

Verification is the bottleneck…. ….and could be a nightmare Multi-Million-Gate Verification • Moore’s Law • Faster and more complex designs • Test-vector size grows even faster than design size • Time-to-market pressures will certainly not abate • Clearly conflicts with the need to exhaustively verify a design before sign-off

Funct. Spec Behavioral MV-Boolean Algebra RTL Register-Transfer MV-Boolean Algebra Logic Synth. Gate-level Net. Logic 2V-Boolean Algebra Floorplanning Place & Route Layout Circuit ODEs Manuf. Circ. Technology PDEs, Montecarlo Digital Systems Verification Hierarchy

Verification Techniques Goal: Ensure the design meets its functional (F) and timing (T) requirements at each of those levels of abstraction • Simulation (FT): Build a mathematical model of the components of the design, submit test vectors and solve the equations that give the output as a function of the input and of the models on a computer • Formal Verification (F): Prove mathematically that: • A description has a set of properties • Two descriptions at different levels of abstraction are functionally equivalent

Verification Techniques Goal: Ensure the design meets its functional (F) and timing (T) requirements at each of those levels of abstraction • Static Timing Analysis (T): Analyze circuit’s topological paths and check their timing properties and their impact on circuit delay • Emulation (F): Map the design onto the components of the emulation machine, submit test vectors and check the outputs of the machine possibly physically connecting them to a system • Prototyping (F): Build a hardware implementation of the design and operate it

1x .001x 10x Simulation: Perfomance vs Abstraction Cycle-based Simulator Event-driven Simulator Abstraction SPICE Performance and Capacity

Boolean Simulation: Single-Processor • Event-driven ("time-wheel" or static-ordered) • Delay Model Emphasis (Inertial or Transport) is major differentiator. • Today about 20-50K events/sec/Mip • Cycle-based

Cycle-based simulation • Cycle-based simulators work off of a control and data-flow representation • Treats everything in the design description as either clocked element or zero-delay combinational logic • Advantages • exceptionally fast • same internal representation for both simulation and synthesis • predicted results same as synthesized logic

S t a t e S t a t e C o m b. L o g i c Cycle-based Algorithm • Input design must be completely synchronous • Only evaluate on the clock edge • First: evaluate all combinational logic • Next: latch values into state registers • Repeat on next clock edge clock

Boolean Simulation: Hardware Acceleration • Quickturn-IBM (Cobalt) type • 1M Event/sec. • Requires fairly long compilation time

Emulation • Based on re-programmable FPGA technology. • Only functional verification (no timing verification yet). • Close to implementation performance. • Can boot operating system, give look and feel for final implementation. • Allows hardware-software co-design.

“Prototyping” Techniques in Design Stages Hardware Design Changes Emulation Cost Software Simulation Performance Prototype Replication Flexibility time

Board Level Rapid-Prototyping Environment • Early feedback on customer’s requirements • Early system integration • In-field test on vehicle • Virtual prototyping (co-simulation) and physical prototyping (emulation board)

Simulation vs Formal Methods • Degree of confidence in simulation depends on test vectors selected by the designers • Formal methods most important for implementation verification • Simulation cannot be replaced by formal verification especially for design verification: specifications are often not given in rigorous terms and are not complete

Analog Circuits – A World Apart • Analog circuits’ behavior specified in terms of complex functions: time-domain, frequency-domain, distorsion, noise, power spectra…. • Required accuracy of models much higher than digital • …emerging paradigm: Field Programmable Analog Array for prototyping (and more)

More on Verification…. • System-on-Chip (SoC): Hardware/Software Co-Verification • Mixed-Signal Verification • Physical Issues introduced by DSM technologies

Design Exploration EE249: Embedded Systems Design Hardware Software Digital Analog 241, 244, 219B 240, 242 Design 247 219C Verification 219A Classes at Berkeley

219A: Course Overview • Fundamentals of Circuit Simulation • Approximately 12 lectures • Analog Circuits Simulation • Approximately 4 lectures • Digital Systems Verification • Approximately 3 lectures • Physical Issues Verification • Approximately 6 lectures

Circuit Simulation • Formulation of circuit equations • STA, MNA • Solution of linear equations • LU factorization, QR factorization, Krylov Methods • Solution of nonlinear equations • Newton’s method • Solution of ordinary differential equations • One-step and Multi-step methods

Analog Circuit Simulation • AC Analysis and Noise • Simulation Techniques for RF • Shooting-Newton • Harmonic-Balance

Digital Systems Verification • Overview • Cycle-based and event-driven simulation • Formal methods • Timing Analysis • Hardware Description Languages (Verilog-VHDL) • System C

Digital Systems VerificationTiming Analysis • Not only has the design to “function properly”….it also has always tighter timing constraints • Design timing properties have to be verified  Static Timing Analysis is the main method

Physical issues verification (DSM) • Interconnects • Signal Integrity • P/G integrity • Substrate coupling • Crosstalk • Parasitic Extraction • Reduced Order Modeling • Manufacturability and Reliability • Power Estimation

Physical issues verification (DSM)Interconnects • Scaling technology • They get longer and longer • Increasing complexity • New materials for low resistivity  Inductance and capacitance become more relevant • Larger and larger impact on the design  Need to model them and include them in the design choices (gate-centric to interconnect-centric paradigm)

Physical issues verification (DSM)P/G and Substrate • Analog and Digital blocks may share supply network and substrate • Can I just plug them together on the same chip? Will it work? • The switching activity of digital blocks injects noise current that may “kill” analog sensitive blocks Digital IP Analog

Physical issues verification (DSM)Crosstalk In DSM technologies, coupling capacitance dominates interlayer capacitance  there is a “bridge” between interconnects on the same layer….they interfere with each other!

Physical issues verification (DSM)Parasitic Extraction • Parasitics play a major role in DSM technologies • Need to properly extract their value and model

Physical issues verification (DSM)Reduced Order Modeling • Increasing complexity  bigger and more complex models • E.g. supply grid, parasitics… • Need to find a “reduced” model so that • Still good representation • Manageable size

Physical issues verification (DSM)Manufacturability • Design a chip • Send it to fabrication • ……. • Did I account for the fabrication process variations? • How many of my chips will work? • Just one? All? Most of them? • How good is my chips performance? Design and verification need to account for process variations!

Physical issues verification (DSM)Reliability • Design a chip • Send it to fabrication • ……. • Did I test my design for different kinds of stress? • Is it going to work even in the worst case? • Can I sell it both in Alaska and Louisiana?

Physical issues verification (DSM)Power Estimation • Advent of portable and high-density circuits  power dissipation of VLSI circuits becomes a critical concern Accurate and efficient power estimation techniques are required

Emerging Paradigm • Design and Verification Integration (Correct by Construction Paradigm) • Hardware and Software Co-verification • <Gone are the days of throwing code "over the wall" to another group. Productive verification requires tearing down the wall between design and verification and between hardware and software.> By Tom Fitzpatrick, Co-Design Automation, Inc., Los Altos, CA EETimes, May 28, 2002

Computer-Aided Verification of Electronic Circuits and Systems