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ISA II

ISA II. Microprocessor without Interlocked Piped Stages Million Instructions Per Second Meaningless indicator of Performance. 0 1 2 3. Aligned. Not Aligned. Addressing Objects: Endianess and Alignment.

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ISA II

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  1. ISA II Microprocessor without Interlocked Piped Stages Million Instructions Per Second Meaningless indicator of Performance

  2. 0 1 2 3 Aligned Not Aligned Addressing Objects: Endianess and Alignment • Big Endian: address of most significant byte = word address (xx00 = Big End of word) • IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA • Little Endian: address of least significant byte = word address (xx00 = Little End of word) • Intel 80x86, DEC Vax, DEC Alpha (Windows NT) little endian byte 0 3 2 1 0 lsb msb 0 1 2 3 big endian byte 0 Alignment: require that objects fall on address that is multiple of their size.

  3. 3 different instruction formats I-type, R-type, MIPS Assembly Language:Instruction Set

  4. R-type Three register operands Arithmetic & logical opcodes Format: Rd = destination operand (output) Rs = source operand (input) Rt = source operand (input) R-type instructions

  5. I-type Two registers and an immediate Format: Rt = destination operand Rs = source operand Immediate = a constant, also a source operand Note: immediate operand must fit into 16 bits! (Why?) I-type instructions.

  6. I-type: 4 fields I-type at work ADDI $2,$1,32 LUI $7,OxABCD I-type instructions contd…

  7. Flow control instructions

  8. Unconditional Branch

  9. Unconditional jump

  10. example

  11. Branch formats

  12. Unconditional Branch • J label • transfer control unconditionally to instruction following label • Ex. loop: add $t1,$s3,$s3 sw $t1,8($s4) j loop Why is the above code segment poor programming?

  13. $s0==$s1? c < 7? Yes Yes label23 label17 No No Conditional Branches Ex 1: Ex 2:

  14. Conditional Branches Ex 3: if (i==j) f=f-i; else f=g+h;

  15. Branching far away…. • 26 bit field in jump instructions is a word address • It represents a word address • Due to the fact that instructions are located at multiples of 4, the 2 LSbits are always 00 !!!!!! • Implicit and can be dropped • CPU appends the 2bits back on the instruction when instruction is fetched and decoded.

  16. For & While Loops Using Arrays • Ex. clear an uninitialized array • int arrayA[100]; • for (i=0; i<100; i++) arrayA[i] = 0; • Let • i = $S3 • base addr. of A = $S4 • 100 = $t1

  17. For & While Loops Using Arrays .data arrayA: .space 400 … … .text LI $t1,100 # load count MOVE $s3,$zero # i = 0 LA $s4,arrayA # load base addr. of A LOOP: BGE $s3,$t1,DONE # done? ADD $t2,$s3,$s3 # i  2 * i ADD $t2,$t2,$t2 # double again ADD $t2,$t2,$s4 # ArrayA[i] SW $zero,0($t2) # ArrayA[i] ADDi $s3,$s3,1 # i++ J LOOP DONE: Int: mult By 4

  18. Addressing Mode

  19. Memory is a linear array of bytes Used to store programs and data Memory is numbered in bytes MIPS can access up to 232 bytes i.e. from 0000000016 to FFFFFFFF16 range of _______ to _______(??Bytes) Note: addresses are always unsigned Variable Declarations

  20. Every memory cell has two attributes address (location) contents Note: Recall registers are accessed by name Note: We may give a location a name for convenience Variable Declarations 5F89025C16 84302B9416 sum

  21. In MIPS, two types of memory accesses are supported 1. Load Register with contents of a memory cell 2. Store Register into a memory cell Variable Declarations Reg Memory Reg

  22. In MIPS, 3 cell sizes can be accessed: byte lb halfword (2 bytes) sh word (4 bytes) lw All accesses must be aligned addresses of words must be divisible by 4 addresses of halfwords must be divisible by 2 bytes are always aligned Variable Declarations

  23. In assembly language, we need to allocate memory for use by program assign names to memory locations (declare variables) initialize memory .data # start of data declarations Data Allocation

  24. To allocate uninitialized memory, use .space To allocate initialized memory, use .byte, .half, .word, .ascii, .asciiz To assign names to locations, prepend allocation directive with a label Data Allocation

  25. Examples Data Allocation .byte 7 # allocate byte and put a 7 in it .half 15 # allocate halfword and put a 15 in it .word 9 # allocate word and put a 9 in it

  26. Ex. (assume we start at address 0 after .data directive) Data Allocation 0 a: .word 0xab b: .word 0x1234 c: .word 0x12345678 a = b = c = Symbol Table:

  27. Can also draw memory in words a: 0 b: 4 c: 8 Data Allocation a: .word 0xab b: .word 0x1234 c: .word 0x12345678

  28. Multiple numeric values separated by commas indicate repeat of directive Useful for small initialized arrays Ex.: Data Allocation a: .word 1 .word 2 .word 3 b: .word 4 .word 5 a: .word 1,2,3 b: .word 4,5

  29. Memory Map a: 0 b: 12 Data Allocation a: word 1,2,3 b: word 4,5

  30. Ex. Data Allocation .data datanums: .byte 1,2,3,4 datanums: 0

  31. Words are said to be aligned if they begin on a 4 byte boundary. Halfwords are said to be aligned if they begin on a 2 byte boundary Bytes are always aligned! Alignment in MIPS

  32. Default in MIPS is ALIGNED memory allocation i.e.  .word means allocate at next quad address (divisible by 4)  .half means allocate at next even address (divisible by 2) When you skip locations, they are uninitialized Alignment in MIPS

  33. Ex. Location Alignment in MIPS 0 .data a: .word 1 b: .byte 2 c: .half 3 d: .byte 4 e: .word 0x12345678 Symbol

  34. Q: Why bother aligning data? A: Because the databus is 32 bits wide. (i.e. memory is accessed on word boundaries.) An unaligned access cannot be done in a single transfer. Alignment in MIPS 0 1 2 3 4 5 12 sum 34 56 78

  35. .space n # allocate n bytes Ex. Uninitialized Allocation: .space a: 0 .data a: .space 4 b: .word 4 c: .space 4 d: .ascii “4”

  36. Ex. Allocating Memory for ASCII Strings string1: 0 .data string1: .ascii “abcdef” string2: .asciiz “abcdef” number1: .word 0x1234 4 Symbol Table: 8

  37. int a,b=5,c[3]={7,8,9}; char string1 = “abcd”; char array1[10]; short int array2[7]; int d=0xAB align manually Allocating Memory: C exampleConvert the C code to MIPSmachine language .data a: .word 0 b: .word 5 c: .word 7 .word 8 .word 9 string1: .asciiz “abcd” array1: .space 10 .space 1 array2: .space 14 d: .word 0xAB auto align

  38. Allocating Memory: C example

  39. Allocating Memory: C example

  40. To get stuff into and out of registers, must use load & store instructions Only way to access memory Memory access => Read or write from or to memory Loading from Memory to RegisterStoring from Register to Memory

  41. Loads Lxx Rt, memory_address e.g. LW $S1,100($S2) Memory[$S2+100]  $S1 Load word from memory location to register Stores Sxx Rt, memory_address e.g. SB $S1,100($S2) $S1  Memory[$S2+100] Store byte from register to memory location Loading from Memory to RegisterStoring from Register to Memory

  42. Load get contents of appropriate # of bytes from memory starting at address memadd and put into register Rt starting with low order.  if # of bytes < 4, then fill high order with 0’s or sign as indicated by instruction Note: loads always affect the entire register! (=> sign extension) Loading from Memory to Register

  43. List of load instructions LW load word (4 bytes) LH load half word (2bytes) -- fill high order with sign LHU load half word (2bytes) -- fill high order with 0’s LB load byte (1 byte) -- fill high order with sign LBU load byte (1 byte) -- fill high order with 0’s Loading from Memory to Register

  44. Store  List of store instructions SW store word (4 bytes) SH store half word (2bytes) SB store byte (1 byte) Storing from Register to Memory Store appropriate # of bytes from Rt, (starting with low order) into memory starting at address memadd

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