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The High Voltage/High Power FET (HiVP)

The High Voltage/High Power FET (HiVP). Amin K. Ezzeddine & Ho C. Huang Amcom Communications, Inc. Clarksburg, Maryland, USA. Presentation Outline. Why high voltage device? Traditional high voltage approaches New Hi gh V oltage/ High P ower ( HiVP ) configuration

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The High Voltage/High Power FET (HiVP)

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  1. The High Voltage/High Power FET (HiVP) Amin K. Ezzeddine & Ho C. Huang Amcom Communications, Inc. Clarksburg, Maryland, USA

  2. Presentation Outline • Why high voltage device? • Traditional high voltage approaches • New High Voltage/ High Power (HiVP) configuration • Implementation of a 14V & 28V GaAs MMIC HiVP • Conclusion

  3. Why High Voltage Device? • Some applications need high voltage: • Phase arrays • Satellite transmitters • No DC-to-DC converter • Low breakdown voltage in semiconductors materials such as: GaAs, AlGaAs, InP. • High power

  4. FET High Voltage Configurations • Traditional high voltage device configurations: • DC series/ RF parallel • DC series/ multi-stage • New High Voltage/high Power device (HiVP)

  5. Vdd = 4Vds INPUT MATCHING OUTPUT MATCHING 3Vds Choke INPUT MATCHING OUTPUT MATCHING 2Vds RF IN RF OUT Power Divider Power Combiner INPUT MATCHING OUTPUT MATCHING Vds Bypass INPUT MATCHING OUTPUT MATCHING Vgg DC Series/RF Parallel Configuration

  6. 2Vds Choke Vds RF in INPUT MATCING OUTPUT MATCHING INTERSTAGE MATCHING Bypass Choke Vgs DC-Series/Cascaded-Stages Configuration RF out

  7. New High Voltage/ High Power (HiVP) • Equivalent performance to a single device:- Efficiency- Power • Higher gain • High voltage bias • Scaled I-V characteristics • Power combiner

  8. Vdd = 4Vds R4 RF OUT OUTPUT MATCHING Vg4=3Vds+Vgs FET4 (W/4) C3 R3 Vd3=3Vds Vg3=2Vds+Vgs FET3 (W/4) C2 R2 Vd2=2Vds Vg2=Vds+Vgs FET2 (W/4) C1 R1 Vd1=Vds RF IN Vg1=Vgs INPUT MATCHING FET1 (W/4) Vgs 4-Cell High Voltage/ High Power (HiVP)

  9. I-V Characteristics of a 4-Cell (4 x 3mm) HiVP Device

  10. R4 Vdd = 4Vm Zopt C3 R3 Vd3=3Vm C2 Vd2=2Vm R2 C1 Vd1=Vm R1 Vin 4-Cells HiVP Voltage Waveforms

  11. Nth FET (N+1)th FET Source Drain Source Drain Gate Gate Zsource, N Zopt, N = Z source, N+1 CN CN+1 Impedance Optimization of Common Gate FET Z source, N 1/gm (Cgs+ C N) / CN gm is FET transconductance Cgs is FET gate-to-source capacitance Zopt, N+1

  12. HiVP Configuration Features • High voltage bias: Vdd = Vds x N • Lower Current by 1/N factor compared to regular FET with equivalent periphery • Higher optimum output impedance by N2 factor • Higher input impedance • Higher gain by factor of N • Broadband matching • Simple & compact configuration • Concept applicable to LDMOS and MOSFET to achieve very high power

  13. Power & IP3 for 14V Hybrid HiVP at 1GHz P1dB =35dBm Efficiency = 25% IP3 = 45dBm @ 1.0GHz

  14. 14V/2-Cells HiVP MMIC ( 2 x 2mm device) S-Parameters Chip Layout P1dB =31dBm Efficiency = 35% IP3 = 46dBm @ 3.5GHz

  15. Pout & Efficiency of 2 x 2mm HiVP at 3.5GHz

  16. IP3 & IP5 of 2 x 2mm HiVP at 3.5GHz

  17. 28V/4-Cells HiVP MMIC (4 x 1mm device) S-Parameters Chip Layout P1dB =31dBm Efficiency = 32% IP3 = 45dBm @ 1GHz

  18. 28V/4-Cells HiVP in Parallel (4 x 3mm device) 4 x 3mm Chip Package Device P1dB =35dBm Efficiency = 27% IP3 = 50dBm @ 2.15GHz

  19. Power & Efficiency of 4 x 3mm HiVP at 2.15GHz

  20. IP3 of a 4 x 3mm HiVP at 2.15GHz

  21. IP3 at 2.15GHz for 4 x 3mm HiVP versus 12 mm FET

  22. 24V/4-Cell High Power pHemt HiVP (4 x24mm) P1dB =43dBm Efficiency = 30% IP3 = 57dBm @ 1.5GHz 4 x 24mm Chip 4 x 6mm Chip

  23. Power & Efficiency of 4 x 24mm pHemt HiVP at 1.5GHz

  24. IP3 of 4 x 24mm pHEMT HiVP at 1.5GHz

  25. Conclusion • A simple DC series/RF series device (HiVP) for high voltage operation is presented • This simple new device behaves as an RF combiner • New device has good linearity and broadband performance • HiVP concept could be applied to GaN and Silicon FETs to push the power to kW ranges

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