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EEL 3705 / 3705L Digital Logic Design

EEL 3705 / 3705L Digital Logic Design. Fall 2006 Instructor: Dr. Michael Frank Module #6: Modular Combinational Logic (Thanks to Dr. Perry for the slides). Note to Self. There are still way too many slides in this module! Need to keep working on making it shorter and more concise.

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EEL 3705 / 3705L Digital Logic Design

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  1. EEL 3705 / 3705LDigital Logic Design Fall 2006Instructor: Dr. Michael FrankModule #6: Modular Combinational Logic(Thanks to Dr. Perry for the slides) M. Frank, EEL3705 Digital Logic, Fall 2006

  2. Note to Self • There are still way too many slides in this module! • Need to keep working on making it shorter and more concise M. Frank, EEL3705 Digital Logic, Fall 2006

  3. Wednesday, October 10, 2006 • Administrivia: • This week’s lab: • Finish “Top secret code display” (w. K-maps), finish project • Design project #1: Due this Friday!! • Test your designs during a lab period, or in TA office hours • Don’t delay writing the large required amount of documentation! • Homework assignment #3: • Due next Monday (October 16th) • Plan for today: • Show Ping-Pong videogame example, in progress • See module #99, Designs (v.3+) for slides • Start next lecture topic: Modular Combinational Logic M. Frank, EEL3705 Digital Logic, Fall 2006

  4. Modular Combinational Logic Original slides by Dr. Reginald Perry With modifications & additions by Mike Frank M. Frank, EEL3705 Digital Logic, Fall 2006

  5. Decoders • General form: n-to-2n decoder • n inputs, 2n outputs • For each input pattern, one and only one output line will be active. • Uses: • “Minterm generator” • Bit/word-line (memory access) circuit • Code conversion • Demultiplexing (routing) of data M. Frank, EEL3705 Digital Logic, Fall 2006

  6. 1-to-2 Decoder • Truth table shown at right • This one can be implementedby just a simple fan-out andan inverter: y0 y0 x x y1 y1 Circuit schematic Icon M. Frank, EEL3705 Digital Logic, Fall 2006

  7. Recursive Contruction of n-to-2n Decoder out of 1-to-2 and (n−1)-to-2n−1 Decoders w0 …plus 2n AND gates w1 w2 xn−1..1 xn−1..0 2n−1 ANDgates 2n−1 … n−1 2n 2n−1 ANDgates z0 x0 z1 M. Frank, EEL3705 Digital Logic, Fall 2006

  8. 1-to-2, 2-to-4 and 3-to-8 Decodersusing recursive design style in Quartus This is really 4 AND gates in parallel This is really 8 AND gates in parallel M. Frank, EEL3705 Digital Logic, Fall 2006

  9. add a slide on the other recursive composition of 2k-to-(2^(2k)) decoders M. Frank, EEL3705 Digital Logic, Fall 2006

  10. 2 to 4 Decoder – Truth Table • 2 to 4 decoder M. Frank, EEL3705 Digital Logic, Fall 2006

  11. 2 to 4 Decoder Equations M. Frank, EEL3705 Digital Logic, Fall 2006

  12. 2 to 4 Decoder: Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

  13. 2 to 4 Decoder: Block Symbol Symbol Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

  14. 3 to 8 Decoder – Truth Table M. Frank, EEL3705 Digital Logic, Fall 2006

  15. 3 to 8 Decoder Equations M. Frank, EEL3705 Digital Logic, Fall 2006

  16. 3 to 8 Decoder: Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

  17. 3 to 8 Decoder: Block Symbol Symbol Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

  18. Design Example • Using only a 3x8 decoder and two-input OR gates, design a logic circuit which implements the following Boolean equation M. Frank, EEL3705 Digital Logic, Fall 2006

  19. Solution m2 m4 m5 M. Frank, EEL3705 Digital Logic, Fall 2006

  20. 2 to 4 Decoder with Enable M. Frank, EEL3705 Digital Logic, Fall 2006

  21. 2x4 Decoder with Enable • Enable is abbreviated as EN • EN is called a Control Signal • Control Signals can be • Active High Signal • EN = 1 – Turns “ON” Decoder • Active Low Signal • EN=0 – Turns “ON” Decoder M. Frank, EEL3705 Digital Logic, Fall 2006

  22. 2 x 4 Decoder with Active High Enable – Truth Table M. Frank, EEL3705 Digital Logic, Fall 2006

  23. 2 to 4 Decoder with Enable Equations M. Frank, EEL3705 Digital Logic, Fall 2006

  24. 2 to 4 Decoder with Enable Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

  25. 2 to 4 Decoder with Enable Symbol M. Frank, EEL3705 Digital Logic, Fall 2006

  26. 2 x 4 Decoder with Active High Enable – Truth Table (Short hand notation) d = don’t care En has “highest” priority. If En=0, we “don’t care” about x1 or x0 because Y=0 M. Frank, EEL3705 Digital Logic, Fall 2006

  27. 2 x 4 Decoder with Active Low Enable – Truth Table (Short hand notation) d = don’t care En has “highest” priority. If En=1, we “don’t care” about x1 or x0 because Y=0 M. Frank, EEL3705 Digital Logic, Fall 2006

  28. 2 to 4 Decoder with Active Low Enable Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

  29. Design Example • Design a 3x8 decoder using only 2x4 decoders and NOT gates. M. Frank, EEL3705 Digital Logic, Fall 2006

  30. Solution “On” when A=0 “On” when A=1 M. Frank, EEL3705 Digital Logic, Fall 2006

  31. Encoders • Opposite of a decoder • 2n to n encoder • 2n inputs • n outputs • For each input, the circuit will produce an “encoded” output M. Frank, EEL3705 Digital Logic, Fall 2006

  32. Example: 4to 2 Binary EncoderTruth Table Assume only one input high at a time!! M. Frank, EEL3705 Digital Logic, Fall 2006

  33. 4 to 2 Encoder Equations M. Frank, EEL3705 Digital Logic, Fall 2006

  34. Problems with initial design • Q: How do we tell the difference between an input of all 0’s (i.e. X=0) and X=1? • A: Add another output (IA) that indicates that the input is valid. Let’s make IA active low. M. Frank, EEL3705 Digital Logic, Fall 2006

  35. Problems with initial design If IA = 1 => all lines are 0 If IA = 0 => at least one line is 1 • Q: What happens if more than one input is high at the same time? • A: Design a “priority” encoder that will encode the input with the highest priority. • Let’s set X3 with the highest priority, followed by X2, X1, and X0 M. Frank, EEL3705 Digital Logic, Fall 2006

  36. Example: 4to 2 Priority Binary EncoderTruth Table M. Frank, EEL3705 Digital Logic, Fall 2006

  37. Solution 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y1 Y0 M. Frank, EEL3705 Digital Logic, Fall 2006

  38. 4 to 2 Priority Encoder Equations M. Frank, EEL3705 Digital Logic, Fall 2006

  39. Monday, October 16, 2006 • Administrivia: • This week’s lab: • “Electronic Device Test” – PO(2/b), experiment • Design projects are being graded this week • Homework assignment #3 is due tonight • Plan for today: • Finish current topic: • Modular Combinational Logic – MUXes, ALUs M. Frank, EEL3705 Digital Logic, Fall 2006

  40. Multiplexer/Data Selectors MUX Very Important Module!!! M. Frank, EEL3705 Digital Logic, Fall 2006

  41. Multiplexer(MUX)/Data Selector • N to 1 multiplexer (or multiplexor) • N=2k data input lines, D0..(N−1) • k=log2(N) control inputs, S(k−1)..0 • Binary encoding of index of selected data • One output: • This circuit will “connect” just the selected input to the output. • The selected input is specified by decoding the control inputs. M. Frank, EEL3705 Digital Logic, Fall 2006

  42. The Simplest Multiplexer • 2-to-1 multiplexer truth table • Output is a copy of • D0 if S0=0 • D1 if S0=1 Schematic,using 1-to-2Decoder module example 2-to-1 MUX Icon M. Frank, EEL3705 Digital Logic, Fall 2006

  43. General Construction of a 2k-to-1 MUX from a k-to-2k decoder, ANDs, and an OR • This is just a direct generalization of the schematic on the previous slide. F “bussed”OR gate 2k 2k 2k This means 2k ANDgates in parallel k S(k−1)..0 M. Frank, EEL3705 Digital Logic, Fall 2006

  44. Recursive Construction of 2k-to-1 muxfrom two 2k−1-to-1 muxes (& a 2-to-1 mux) 2k−1 k−1 F 2k 2k−1 Sk−1 S(k−2)..0 k−1 S(k−1)..0 k M. Frank, EEL3705 Digital Logic, Fall 2006

  45. 4-to-1 MUX from three2-to-1 MUXes • Try building some larger sizes for yourself… M. Frank, EEL3705 Digital Logic, Fall 2006

  46. Example: 4to 1 MUX Truth Table Control Inputs Output Data Inputs d = don’t care / Di = data on input i M. Frank, EEL3705 Digital Logic, Fall 2006

  47. 4 to 1 MUX Equation D’s are the DATA inputs, AB are control inputs and called the “select” lines. M. Frank, EEL3705 Digital Logic, Fall 2006

  48. 4 to 1 MUX Circuit Control Inputs Data Inputs Output 2x4 Decoder Only a single AND gate will be “ON” at a time. M. Frank, EEL3705 Digital Logic, Fall 2006

  49. 4 to 1 MUX Symbol A more common, and more mnemonic MUX symbol: D0 Data Inputs D1 F Output D2 Control Inputs S1..0 D3 M. Frank, EEL3705 Digital Logic, Fall 2006

  50. Logic with multiplexers • You can implement any n-input logic function with a single 2n-to-1 multiplexer, by feeding appropriate constants into the MUX’s data inputs. • Namely, the list of the function’s output values from its truth table • The multiplexer implements a “lookup table” • it simply looks up the function result from the indicated row of the truth table • Of course, this is generally not the most hardware-efficient way to implement a given function. M. Frank, EEL3705 Digital Logic, Fall 2006

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