1 / 27

COMS 361 Computer Organization

COMS 361 Computer Organization. Title: Instructions Date: 9/21/2004 Lecture Number: 8. Announcements. Homework 3 Due 9/28/04. Review. Instructions MIPS arithmetic instruction format Immediate instructions MIPS load and store instructions Addressing. Outline. Instructions

wynn
Télécharger la présentation

COMS 361 Computer Organization

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. COMS 361Computer Organization Title: Instructions Date: 9/21/2004 Lecture Number: 8

  2. Announcements • Homework 3 • Due 9/28/04

  3. Review • Instructions • MIPS arithmetic instruction format • Immediate instructions • MIPS load and store instructions • Addressing

  4. Outline • Instructions • MIPS load and store instruction format • MIPS immediate instruction format • Addressing • MIPS branch instructions and format

  5. Immediate Instructions • Frequently constants are added during program execution • Increment (i++) • Speed execution if these constants could be in the instruction instead of in memory • MIPS provides an immediate version of some instructions, which contain a constant • C/C++ code i = i + 1; • MIPS code addi $s0, $s1, 1

  6. rs 5 rt 5 rd 5 shamt 5 funct 6 op 6 Immediate Instructions • Syntax is similar to R-type instructions • Except a number needs to be stored in the instruction • Where should the immediate value be put using this instruction format? • Hummmmm

  7. Base register Data Transfer Instructions C/C++ code: b = A[8]; MIPS code: lw $t0, 32($s2) • Data transfer instruction syntax • 1 2, 3(4) 1) Operation (instruction) name 2) Destination register 3) Numerical offset in bytes 4) Register containing the base address of the array register contains a pointer to memory

  8. Data Transfer Instructions lw $t0, 32($s2) • 16-bit address means words within a 215 range around the address in the base register can be loaded • Positive and negative offsets • 16-bit immediate number is the same number of bits as a signed short integer in C/C++ rs rt Address or immediate value op 6 5 16 6

  9. Design Principle 3 • Good design demands good comprises • MIPS comprise • Keep all instructions the same size (32-bits) • Allow different instruction formats for different types of instructions

  10. 35 9 32 18 op rs rt number Machine language • Example: lw $t0, 32($s2) • The effective address (EA) of the word to load is computed as: • Address stored in the $s2 register (the base address) plus the offset amount • Addressing mode is called • register indirect with immediate offset

  11. Machine language • register indirect with immediate offset • EA = register + signed immediate • There are other address schemes used by other architectures, but only this one for MIPS

  12. word address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 8-bit data word 1 word 2 word 3 Pitfall • Forgetting sequential word address in a byte addressable machine differ by the word size (in bytes), not 1 • MIPS is a word aligned machine • Word addresses must be a multiple of 4 • A 32-bit word actually occupies four contiguous locations (bytes) of main memory

  13. Bytes in Word 0 1 2 3 Aligned Not Aligned Word Location Pitfall • 0, 4, 8 and 12 are valid word addresses. • 1, 2, 3, 5, 6, 7, 9, 10 and 11 are not valid word addresses. • Unaligned memory accesses result in a bus error, which you may have unfortunately seen before

  14. Stored Program Concept • Fetch & Execute Cycle • Instructions are fetched (from memory) and put into a special register • Bits in the register "control" the subsequent actions • Fetch the “next” instruction and continue

  15. How is the address of the next instruction determined? Fetch and Execute Cycle

  16. Fetch and Execute Cycle • Sometimes the address of the next instruction to execute is the next word address • Other times it is not • What kind of C++ statement would cause non-sequential instruction execution? if the condition is not true if (condition) { execution jumps to the more blah instruction • blah; • blah; out of sequence instruction execution } • more blah;

  17. A label you create or make up Control Flow • Decision making instructions • Alter the control flow • Change the "next" instruction to be executed • MIPS conditional branch instructions • beq $t0, $t1, EQ • branch if equal • If the contents of register $t0 == $t1 the next instruction to be executed is the one associated with the label EQ • beq $t0, $t1, NEQ • branch if NOT equal • Execute instruction associated with NEQ if the contents of register $t0 != $t1

  18. Control Flow • Example: conditional branch instructions • C/C++ code: if(i == j) { h = i + j; } • MIPS code: bne $s0, $s1, NEQ add $s3, $s0, $s1 NEQ: .... • Notice: in MIPS we reversed the condition to goto NEQ • If the condition is NOT true, skip the next instruction • If the condition is true, execute the next instruction and continue sequential instruction execution

  19. Conditional Branch Instructions • The conditional branch instructions require • 1 2, 3, 4 • 1 is the op code for the instruction • 2 is the first operand (register address) • 3 is the second operand (register address) • 4 is the target address • Actually it is an offset amount from the current instruction • Can be positive or negative • Branch later in the code • Branch earlier in the code (previous statements)

  20. 5 18 25 17 op rs rt number Conditional Branch Instructions • Sounds like conditional branch instructions can utilize the: • I-type format

  21. Conditional Branch Instructions • C++ code: if (i == j) { f = g + h; } else { f = g – h; } • MIPS code: bne $s3, $s4, Else add $s0, $s1, $s2 Else: sub $s0, $s1, $s2 • But of course there is a problem here • The instruction with the Else label is executed regardless of the condition value • Need to unconditionally branch to a label

  22. Control Flow • MIPS also provides an unconditional branch instruction: • j label • Introduce a new type of instruction format • j-type for branch instructions

  23. Control Flow • C++ code: if (i == j) { f = g + h; } else { f = g – h; } • MIPS code: bne $s3, $s4, Else add $s0, $s1, $s2 j Endif Else: sub $s0, $s1, $s2 Endif:blah beq $s4, $s5, EQ sub $s3, $s4, $s5 j Endif EQ: add $s3,$s4,$s5 Endif:blah

  24. Address Op code Control Flow • Unconditional branch instruction requires only an op code and an address to jump to

  25. Control • Can you build a simple for loop in MIPS assembly language?

  26. Summary so far • InstructionMeaning • add $s1,$s2,$s3 $s1 = $s2 + $s3 • sub $s1,$s2,$s3 $s1 = $s2 – $s3 • lw $s1,100($s2) $s1=Memory[$s2+100] • sw $s1,100($s2) Memory[$s2+100]=$s1 • bne $s4,$s5,LNext instr. is at L if $s4 != $s5 • beq $s4,$s5,LNext instr. is at Label if $s4 == $s5 • j LabelNext instr. is at Label

  27. R op rs rt rd shamt funct I op rs rt 16 bit address J op 26 bit address Summary so far • Instruction formats

More Related