Understanding Transistor Fabrication and Behavior in 180 nm Technology
This comprehensive guide explores the fundamentals of transistor fabrication using 180 nm technology, detailing the fabrication steps, structure types, and basic transistor behavior. It covers essential concepts such as the effects of n-type and p-type doping, the significance of photolithography, and the challenges of latch-up in CMOS integrated circuits. Utilizing typical parameters for a 1.2V supply voltage, we delve into current characteristics and parasitics. This resource aims to provide educational insights suitable for those engaged with semiconductor technology.
Understanding Transistor Fabrication and Behavior in 180 nm Technology
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Presentation Transcript
Topics • Basic fabrication steps. • Transistor structures. • Basic transistor behavior. • Latch up.
Our technology • We will study a generic 180 nm technology. • Assume 1.2V supply voltage. • Parameters are typical values. • Parameter sets/Spice models are often available for 180 nm, harder to find for 90 nm.
Fabrication services • Educational services: • U.S.: MOSIS • EC: EuroPractice • Taiwan: CIC • Japan: VDEC • Foundry = fabrication line for hire. • Foundries are major source of fab capacity today.
Fabrication processes • IC built on silicon substrate: • some structures diffused into substrate; • other structures built on top of substrate. • Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) • Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). • Silicon dioxide (SiO2) is insulator.
transistor via Simple cross section SiO2 metal3 metal2 metal1 poly substrate n+ n+ p+ substrate
Photolithography Mask patterns are put on wafer using photo-sensitive material:
Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub p-tub substrate
Process steps, cont’d. Pattern polysilicon before diffusion regions: gate oxide poly poly p-tub p-tub
Process steps, cont’d Add diffusions, performing self-masking: poly poly p-tub n+ n+ p-tub p+ p+
Process steps, cont’d Start adding metal layers: metal 1 metal 1 vias poly poly p-tub n+ n+ p-tub p+ p+
Transistor structure n-type transistor:
0.25 micron transistor (Bell Labs) gate oxide silicide source/drain poly
Transistor layout n-type (tubs may vary): L w
Drain current • Linear region (Vds < Vgs - Vt): • Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5Vds2) • Saturation region (Vds >= Vgs - Vt): • Id = 0.5k’ (W/L)(Vgs - Vt) 2
180 nm transconductances Typical values: • n-type: • kn’ = 170 A/V2 • Vtn = 0.5 V • p-type: • kp’ = 30 A/V2 • Vtp = -0.5 V
Current through a transistor Use 180 nm parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. • Vgs = 0.7V: Id = 0.5k’(W/L)(Vgs-Vt)2= 5.3 A • Vgs = 1.2V: Id = 62 A
Basic transistor parasitics • Gate to substrate, also gate to source/drain. • Source/drain capacitance, resistance.
Basic transistor parasitics, cont’d • Gate capacitance Cg. Determined by active area. • Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. • Cgs = Col W • Gate/bulk overlap capacitance.
Latch-up • CMOS ICs have parastic silicon-controlled rectifiers (SCRs). • When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. • Early CMOS problem. Can be solved with proper circuit/layout structures.
Parasitic SCR circuit I-V behavior
Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.
Tub tie layout p+ metal (VDD) p-tub
