Wireless Terminal and PC Interface Using VLSI

1. Wireless Terminal and PC Interface Using VLSI EE452 - Senior Project Members: Chris Brophy Matt Olinger Advisor: Dr. V. Prasad 5/2/02

2. Abstract • Uses ISA (Industry Standard Architecture) interface and off-the-shelf wireless RF module • Design and testing accomplished with Logic Works, Emac 8051 Development Board, Renoir, ModelSim, Xilinx CPLD, and L-EDIT • Provides alternative to costly internet providers – low cost, short range transmissions

3. Outline • Design Overview • Pin Count • Block Diagram • Testing • Logic Works, Renoir, CPLD (Complex Programmable Logic Device), Emac • Implementation / Problems • Future Improvements • Schedule • References

4. Design Overview • Two interfaces are required: • ISA bus (from computer) • Proprietary bus interface (RF device) • A method of buffering is also necessary, since the data rates of both interfaces are unequal. • A status register is also necessary to provide feedback to the computer when to send and receive. • Timing is critical!

5. Pin Count • 26 / 34 pins used • ISA interface • Data D0-D7 • Address A0-A9 • IOW, IOR, INT, BCLK • RF module (Linx Tech) • RX enable, TX enable • Serial Data (RX and TX) Typical MOSIS Pad

6. Block Diagram

7. Hardware Flowchart

8. Testing • Logic Works • Component level simulation • Emac 8051 Development Board - Keil • Test RF module • Communication protocol • Xilinx CPLD – Renoir / ModelSim • ISA bus timing tester • Component level design

9. Address Decoding – Logic Works

10. Address Decoder - Renoir

11. Address Decoder - VLSI

12. Shift Register – Logic Works

13. Shift Register - Renoir

14. Shift Register – VLSI

15. 9 Bit Counter – Logic Works

16. 9 Bit Counter – Renoir

17. Shift Counter – Logic Works

18. Shift Counter – Renoir

19. Combination – Renoir

20. ISA bus timing simulation – ModelSim

21. VHDL Testing Computer ISA development board and Xilinx CPLD Linx RF transceiver

22. EMAC Testing • Serial Transmission Testing • Assembly code emulates serial transmission to and from the RF module

23. Implementation / Problems • EMAC • Transmitter and Receiver Code • Renoir / FPGA • Large learning curve using Renoir • Xilinx XC4200 cannot implement flip flops with both asynchronous set and reset • CPLD implementation • Software deficiencies, Address line loading, grounding

24. Future Improvements • Newer bus • PCI (Peripheral Component Interconnect) or USB (Universal Serial Bus) • ISA bus is obsolete • Plug and Play allows easy configuration • Hardware Error Detection / Correction • Take software responsibility from CPU • Larger Buffer / Shift Register • Send information as packets • Less time wasted during TX/RX transitions

25. Proposed Schedule • Dec – Jan (Break) • More “preliminary” design work (Begin Logic Gates) • Feb • Finish Logic Design • Begin Simulation • March • Finish Simulation / Begin drawing in LEDIT • Implement design on FPGA / CPLD • April • Finish drawing gates in LEDIT / Present at Expo

26. References Solari, Edward. ISA and EISA Theory and Operation. Annabooks, 1994. Mazidi, Muhammad Ali. The 80x86 IBM PC and Compatible Computers Third Ed. Prentice-Hall Inc., 2000. www.xilinx.com Renoir Architecture Tutorial (http://cegt201.bradley.edu/tutorial/)

27. QUESTIONS? Visit http://cegt201.bradley.edu/projects/proj2002/asdf