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Virtual Memory

Virtual Memory. Outline. Address translation Accelerating translation with a TLB Multilevel page tables Suggested reading: 10.6. Address Translation. V = {0, 1, . . . , N –1} virtual address space P = {0, 1, . . . , M –1} physical address space N > M Address Translation

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Virtual Memory

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  1. Virtual Memory

  2. Outline • Address translation • Accelerating translation • with a TLB • Multilevel page tables • Suggested reading: 10.6

  3. Address Translation • V = {0, 1, . . . , N–1} virtual address space • P = {0, 1, . . . , M–1} physicaladdress space • N > M • Address Translation • MAP: VP U {} address mapping function • MAP(a) = a' if data at virtual address a is present at physical address a' in P =  if data at virtual address a is not present in P (invalid or on disk)

  4. page fault fault handler Processor  Hardware Addr Trans Mechanism Secondary memory Main Memory a a' OS performs this transfer (only if miss) virtual address physical address part of the on-chip memory mgmt unit (MMU) Address Translation

  5. Address Translation • Basic Parameters • N = 2n= Virtual address limit • M = 2m = Physical address limit • P = 2p = page size (bytes).

  6. n–1 p p–1 0 virtual address virtual page number page offset address translation m–1 p p–1 0 physical address physical page number page offset Notice that the page offset bits don't change as a result of translation Address Translation

  7. Address Translation • Basic Parameters • N = 2n= Virtual address limit • M = 2m = Physical address limit • P = 2p = page size (bytes). • Components of the virtual address (VA) • VPO: Virtual page offset • VPN: Virtual page number • Components of the physical address (PA) • PPO: Physical page offset (same as VPO) • PPN: Physical page number

  8. page table base register (PTBR) virtual address n–1 p p–1 0 VPN acts as table index virtual page number (VPN) page offset physical page number (PPN) access valid if valid=0 then page not in memory m–1 p p–1 0 physical page number (PPN) page offset physical address Address Translation via Page Table

  9. 10 7 4 5 6 10 8 9 2 12 13 3 11 11 0 0 1 2 3 4 1 6 7 8 9 5 VPN VPO PPO PPN (Virtual Page Offset) (Virtual Page Number) (Physical Page Number) (Physical Page Offset) Simple Memory System Example • Addressing • 14-bit virtual addresses • 12-bit physical address • Page size = 64 bits (6-bit)

  10. Simple Memory System Page Table • Only show first 16 entries

  11. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPN VPO 4 5 6 7 8 9 1 11 3 2 0 10 PPN PPO Address Translation Example Virtual Address: 0x03D4 VPN: VPO: Page Fault? d PPN: PPO: PA:

  12. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPN VPO 6 1 2 3 4 5 7 8 11 0 9 10 PPO PPN Address Translation Example Virtual Address: 0x03D4 0 0 0 0 1 1 1 1 0 1 0 1 0 0 VPN: 0x0fVPO: 0x14 Page Fault? d PPN: PPO: 0x14 PA:

  13. Simple Memory System Page Table • Only show first 16 entries

  14. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPN VPO 8 9 7 6 5 4 3 11 1 0 10 2 PPN PPO Address Translation Example Virtual Address: 0x03D4 0 0 0 0 1 1 1 1 0 1 0 1 0 0 VPN: 0x0fVPO: 0x14 Page Fault? No d 0 0 1 1 0 1 0 1 0 1 0 0 PPN: 0x0D VPO: 0x14 PA: 0x

  15. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPN VPO 8 9 7 6 5 4 3 11 1 0 10 2 PPN PPO Address Translation Example Virtual Address: 0x03D4 0 0 0 0 1 1 1 1 0 1 0 1 0 0 VPN: 0x0fVPO: 0x14 Page Fault? No d 0 0 1 1 0 1 0 1 0 1 0 0 PPN: 0x0D VPO: 0x14 PA: 0x354

  16. VA: virtual address PTEA: page table entry address PTE: page table entry PA: physical address Page Hit 2 Cache/ Memory CPU Chip PTEA MMU 1 PTE CPU VA 3 PA 4 Data 5 1) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor

  17. Page Faults Exception Page fault handler 4 2 Cache/ Memory Disk CPU Chip Victim page PTEA MMU 1 5 VA PTE CPU 3 7 New page 6 1) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in memory 4) Valid bit is zero, so MMU triggers page fault exception 5) Handler identifies victim (and, if dirty, pages it out to disk) 6) Handler pages in new page and updates PTE in memory 7) Handler returns to original process, restarting faulting instruction

  18. miss VA PA Trans- lation Cache Main Memory CPU hit data Integrating Caches and VM

  19. Integrating Caches and VM • Most Caches “Physically Addressed” • Accessed by physical addresses • Allows multiple processes to have blocks in cache at same time • Allows multiple processes to share pages • Cache doesn’t need to be concerned with protection issues • Access rights checked as part of address translation

  20. Integrating Caches and VM • Perform Address Translation Before Cache Lookup • But this could involve a memory access itself (of the PTE) • Of course, page table entries can also become cached

  21. Integrating Caches and VM PTE CPU Chip PTE PTEA hit MMU Memory PTEA PTEA miss PTEA CPU VA PA PA miss PA Data PA hit L1 cache Data

  22. Speeding up Translation with a TLB • “Translation Lookaside Buffer” (TLB) • Small hardware cache in MMU • Maps virtual page numbers to physical page numbers

  23. TLB Hit CPU Chip TLB PTE 2 3 VPN Cache/ Memory MMU 1 PA VA CPU 4 Data 5 A TLB hit eliminates a memory access

  24. TLB Miss CPU Chip TLB 4 PTE 2 VPN Cache/ Memory MMU 1 3 VA PTEA CPU PA 5 Data 6 A TLB miss incurs an additional memory access (PTE)Fortunately, TLB misses are rare. Why?

  25. Speeding up Translation with a TLB

  26. Address Translation n–1 p p–1 0 virtual address virtual page number page offset TLB tag TLB index address translation m–1 p p–1 0 physical address physical page number page offset Cache tag Cache index Cache offset

  27. Address Translation • Components of the virtual address (VA) • VPO: Virtual page offset • VPN: Virtual page number • TLBI: TLB index • TLBT: TLB tag • Components of the physical address (PA) • PPO: Physical page offset (same as VPO) • PPN: Physical page number • CO: Byte offset within cache line • CI: Cache index • CT: Cache tag

  28. Speeding up Translation with a TLB n–1 p p–1 0 virtual address virtual page number page offset valid tag physical page number . . . TLB = TLB hit physical address physical page number page offset tag index valid tag data Cache = data cache hit

  29. TLBI TLBT 7 13 12 11 10 8 9 6 4 3 2 1 0 5 VPO VPN Simple Memory System TLB • Addressing • 14-bit virtual addresses • 12-bit physical address • Page size = 64 bits (6-bit) • TLB • 16 entries • 4-way associative (2-bit)

  30. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 VPN VPO 4 5 6 7 8 9 11 3 1 0 10 2 PPN PPO 0 0 1 1 0 1 0 1 0 1 0 0 Address Translation Example Virtual Address 0x03D4 VPN: 0x0f TLBI: 0x03 TLBT: 0x03TLB Hit? Page Fault? O PPN: PPO: PA:

  31. TLBI TLBT 7 13 12 11 10 8 9 6 4 3 2 1 0 5 VPO VPN Simple Memory System TLB • Addressing • 14-bit virtual addresses • 12-bit physical address • Page size = 64 bits (6-bit) • TLB • 16 entries • 4-way associative (2-bit)

  32. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 VPN VPO 4 5 6 7 8 9 11 3 1 0 10 2 PPN PPO 0 0 1 1 0 1 0 1 0 1 0 0 Address Translation Example Virtual Address 0x03D4 VPN: 0x0f TLBI: 0x03 TLBT: 0x03TLB Hit? YesPage Fault? No PPN: 0x0D PPO: 0x14 PA: 0x354

  33. CO CI CT 3 6 11 10 9 8 4 5 2 1 0 7 PPO PPN Simple Memory System Cache • Cache • 16 lines • 4-byte line size • Direct mapped

  34. CO CI CT 11 10 9 8 7 6 5 4 3 2 1 0 PPO PPN 0 0 1 1 0 1 0 1 0 1 0 0 Address Translation Example PA: 0x354 • Offset: 0x0 CI: 0x05 CT: 0x0D Hit? Byte: 0x 6

  35. CO CI CT 3 6 11 10 9 8 4 5 2 1 0 7 PPO PPN Simple Memory System Cache • Cache • 16 lines • 4-byte line size • Direct mapped

  36. CO CI CT 11 10 9 8 7 6 5 4 3 2 1 0 PPO PPN 0 0 1 1 0 1 0 1 0 1 0 0 Address Translation Example PA: 0x354 • Offset: 0x0 CI: 0x05 CT: 0x0D Hit? YesByte: 0x36

  37. Multi-Level Page Tables • Given: • X86: 32-bit address space 4KB (212) page size, 4-byte PTE • X86-64: 48-bit address space 4KB (212) page size, 8-byte PTE • Problem: • X86: Would need a 4 MB page table! • 220 *4 bytes (20bit = 32bit – 12bit) • X86-64: Would need a 512 GB page table! • 230 *8 bytes (30bit = 48bit – 12bit)

  38. Level 2 Tables Level 1 Table ... Multi-Level Page Tables • Common solution • multi-level page tables • e.g., 2-level page table • Level 1 table: 1024 entries, each of which points to a Level 2 page table. • Level 2 table: 1024 entries, each of which points to a page

  39. Multi-Level Page Tables Virtual memory Level 1 page table Level 2 page tables 0 VP 0 ... PTE 0 PTE 0 VP 1023 2K allocated VM pages for code and data ... PTE 1 VP 1024 PTE 1023 PTE 2 (null) ... PTE 3 (null) VP 2047 PTE 4 (null) PTE 0 Gap PTE 5 (null) ... PTE 6 (null) PTE 1023 6K unallocated VM pages PTE 7 (null) PTE 8 1023 null PTEs (1K - 9) null PTEs PTE 1023 1023 unallocated pages 1023 unallocated pages 1 allocated VM page for the stack VP 9215 32 bit addresses, 4KB pages, 4-byte PTEs ...

  40. Multi-Level Page Tables

  41. Summary • Programmer’s view of virtual memory • Each process has its own private linear address space • Cannot be corrupted by other processes • System view of virtual memory • Uses memory efficiently by caching virtual memory pages • Efficient only because of locality • Simplifies memory management and programming • Simplifies protection by providing a convenient interpositioning point to check permissions

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