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Mars Atmosphere and Volatile EvolutioN (MAVEN) Mission PowerPoint Presentation
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Mars Atmosphere and Volatile EvolutioN (MAVEN) Mission

Mars Atmosphere and Volatile EvolutioN (MAVEN) Mission

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Mars Atmosphere and Volatile EvolutioN (MAVEN) Mission

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  1. Mars Atmosphere and Volatile EvolutioN (MAVEN) Mission Solar Wind Electron Analyzer (SWEA) Critical Design Review May 23 -25, 2011 Dave Mitchell SWEA Lead

  2. IRAP / UCB-SSL Collaboration • SSL, Berkeley • Pedestal • Digital / FPGA • LVPS (same as for STEREO SWEA) IRAP (CESR), Toulouse • Analyzer • MCP • Anode • HVPS

  3. SWEA Team – SSL • David L. Mitchell (Instrument Lead) • Paul Turin (Mechanical) • Ellen Taylor (Electrical) • Chris Smith (Thermal) • with support from John Hawk at NASA-GSFC • Dorothy Gordon (FPGA) • Peter Harvey (FSW [PFDPU]) • Peter Berg, Selda Heavner (Power Supplies) • Tim Quinn (GSE) • Steve Marker (Facilities) • Daniele Meilhan (Scheduling) • Kate Harps, Jim Keenan, Misty Willer (Purchasing, Contracts)

  4. SWEA Team – IRAP • Christian Mazelle (Lead Co-I) • Jean-Jacques Thocaven (PM, Electronics) • Jean-André Sauvaud, Dominique Toublanc (Co-Is) • Jean Rouzaud (Mechanics, Environmental tests) • Andrei Fedorov (Detector simulations, Calibrations) • Philippe Rouger (Electronics) • Eric Lecomte (Integration, Coating) • Qiu Mei Lee (Documentation) • David Moirin BTS Industrie (Quality Assurance) • TBD (CNES Technical Assistance for AIT) starting in April. • Claude Aoustin (former CESR Technical Manager, expert) • punctual assistance by Jean-Louis Médale (retired; expert on electronics) • CNES can bring expert persons on request (components, EMC…)

  5. SWEA Documentation • Performance Requirements • MAVEN-PM-RQMT-0005, Mission Requirements (Level 2) • MAVEN-PFIS-RQMT-0016, PFP Requirements (Level 3) • MAVEN-PF-SWEA-002, SWEA Specification (Level 4) • Differences from STEREO SWEA • SWEA_STEREOtoMAVENChanges • Interface Documents • MAVEN-PF-SWEA-001I_CESRtoSSLICD (analyzer to pedestal) • MAV-SWE-ICD-001 SWEA MICD (pedestal to spacecraft) • MAVEN_PF_SYS_0xx, PFP interfaces and specifications • Environments • MAVEN-SYS-RQMT-0010 (Environmental Requirements Document) • MAVEN_ESC_specification (electrostatic cleanliness) • Software • MAVEN_PF_FSW_002 • MAVEN_PF_SWEA_012A_FPGA_Specification (Level 5)

  6. SWEA pre-CDR Peer Review Held at IRAP, Toulouse, March 28-29 PFPRRFA01: Planetary Protection Implementation Plan – STATUS: Submitted Statement of Concern: IRAP may be unnecessarily implementing more PP activities than MAVEN required and using resources that they may want to apply elsewhere. Recommended Action: Clarify the required PP activities and update the PFP Contamination Control Plan to reflect what will be done Originator: N. Jedrich / GSFC PFPRRFA02: Assays – STATUS: Submitted Statement of Concern: Assays, as part of planetary protection implementation, and the analysis of the samples is not well defined. Recommend Action: Define, in the SSL contamination plan, who will take the assays, how often, and where they will be analyzed during AIT at IRAP. Originator: N. Jedrich / GSFC

  7. SWEA Science David L. Mitchell May 24, 2011

  8. MAVEN Level 1 Requirements

  9. SWEA Science Goals • Magnetic Topology & Plasma Regime • Crustal Magnetospheres/Cusps • Draped Field Lines o o o

  10. SWEA Science Goals MGS MAG/ER • Electron Impact Ionization • Magnetic Pileup Region • Ionosphere

  11. SWEA Science Goals Mars Express Shadow 2.35 RM Photo-ionization of CO2by solar h @ 304 Å ESCAPE PEB h-electrons MPB 5 4 3 R (MSO) 2 1 0 Escape associated with heavy ions (M> 16) -3 -2 -1 0 1 2 X (MSO)

  12. of the sensor at low energy can be controlled by varying the voltage bias U0 between the internal and external grids: where is the energy resolution for zero bias (0.175) and is the incident energy of the electron Thus for 1.5x finer energy resolution (and 2x smaller GF), we apply Variation of Energy Resolution* *Not needed to meet Level 3 requirements / Works for apoapsis and side segments in all orbit scenarios. Works for Sun-Velocity mode at periapsis (~50% of orbits). Does not work for deep dips.

  13. PF Level 3 Requirements

  14. In-Flight Calibration • Pre-launch: SWEA must have the right dynamic range to handle expected flux range at Mars (10 years of experience with MGS ER) • The energy and angle responses and geometric factor (minus detector efficiency) are determined within ~10% by calibration and simulation. • Detection efficiency depends on MCP efficiency, which varies with time. • In-flight: Absolute START and STOP efficiencies for STATIC are determined in the sheath from event ratios: (START with STOP)Validand (STOP with START)Valid STARTValidSTOPValid Combine this with mechanical analyzer geometric factor from simulations to get absolute sensitivity. • With STATIC as the reference, calibrate SWEA and SWIA by determining total plasma density in the sheath.

  15. Data Products FPGA provides a single science data product to the PFDPU Counts per accumulation interval for each of the 16 anodes (as a function of analyzer and deflector sweeps) Complete measurement sequence takes 2 seconds. PFDPU computes three data products, with cadence depending on altitude

  16. Spacecraft Accomodation • Boom location: • Separation from s/c potentials • Large, clear field of view • Sensor head in shadow • Electronics box in sunlight FOV: 360o x ±65o SWEA axis parallel to SC Z when deployed

  17. SWEA Resources

  18. SWEA Electrical Ellen Taylor May 24, 2010

  19. SWEA Electronics Overview Block Diagram No major changes since PDR Digital Board Design and EM Verification LVPS Board Design and EM Verification EM Integrated Electronics Test Results Digital Board/Analyzer LVPS/Digital Board LVPS/Digital Board/Analyzer to PFDPU Parts Stress Analysis, Parts Status and Issues Power Budget

  20. SWEA Electrical Block Diagram UCB IRAP/CESR

  21. Heritage and Design Similarities MAVEN SWEA digital board has direct heritage from STEREO SWEA: Minor interface changes (separate connector to SC for temp sensor, heater and actuator, external PFDPU connector) Changed interface logic to 3.3V from 5V (added translators 54ACT244 on FPGA outputs, UT54ACS164245SEI on pre-amp inputs to FPGA) Minor FPGA part change (RT54SX72S from RT54SX32S) Removed STE digital circuitry and interface Removed latch-up circuitry Minor part changes due to obsolescence, desire to have common parts buy and circuitry MAVEN SWEA digital board is very similar to MAVEN SWIA and STATIC: FPGA and SRAM same as SWIA, different than STATIC Housekeeping (HK MUX and ADC parts) same Fixed and Sweep DACs same minus offset DACs need for STATIC

  22. Digital Board Design Command/Data Interface to PFDPU Accumulate counts from each of the 16 anodes Bin data for transfer to PFDPU Enable HVPS and MCP high voltage Control voltage sweeps for analyzer inner hemisphere and deflectors SRAM for storing lookup tables and accumulators Generate test pulses Control ADC and MUX to read instrument housekeeping monitors Note: Digital board does not control heaters (S/C) or cover actuators (S/C)

  23. Digital Board Status Board Built and Loaded (MAVEN-PF-SWE-SCH-001 Rev 16)

  24. Digital Board EM Verification Digital Board Test per MAVEN-SWE-PROC-001 verifies: TLM/CMD connectivity with MISG Power distribution to test points Power consumption by service Power generation (+/-4V reference for DACs) Polarity on all polarized capacitors Analog (raw and converted) and digital housekeeping Test pulser generation and frequency High voltage allow, arm, enable Fixed and Sweep DAC control Anode Count Products (message receipt) Soft Reset

  25. SWEA and SWIA FPGA Similarities Commonalities Both require anode counting frontends Both implement Command & Telemetry Interfaces (CDI functionality for receiving commands and sending messages) Housekeeping Control and Message Format Memory Control Fixed and Sweep DAC Control Timing Backbone (reconfigured to accommodate the different accumulation intervals) Lookup table memory and control (Loader and Checksummer) High Voltage turn-on is a protected command Differences SWIA: 24 Anodes (14 WFOV and 10 NFOV) SWEA: 16 Anodes SWIA: 4 second cycle with 2304 Accumulation Intervals SWEA: 2 second cycle with 488 Accumulation Intervals SWIA Implements Products SWEA Includes Operational Heater Control

  26. FPGA Block Diagram removed, not required • verified pending Rev 2 • verified • verified • verified • verified • (self-test pending Rev2) • verified • verified • verified • verified

  27. SWEA Test Pulser Data

  28. SWEA LVPS Design and Test • DESIGN • Converts regulated +28V from PFDPU to +28VA +/-10% (20mA Peak), +12VA +/-5% (8mA), +5VA +/-5% (10mA), -5VA +/-5% (10mA), -12VA +/-5% (10mA), +5VD +/-5% (40mA), +3.3VD +/-3% (10mA), +2.5VD +/-3% (10mA) • TESTS PERFORMED • Turn on • Voltage Levels • Load regulation • Input Voltage Range Test • Integration w/ Digital Board • ONGOING/FUTURE TASKS • Flight layout • Stability tests • Efficiency test • Thermal test • Test Procedure • Parts Stress Analysis

  29. Integrated Digital/Analyzer Test Digital Board Integrated and Tested with EM Analyzer per MAVEN-PF-SWE-PROC-002: Safe-to-Mate Analog Housekeeping from Analyzer Test Pulser MCP High Voltage Enable MCP HV Control Non-Regulated HV Enable Sweep DAC Control Deflector and Vo Control Anode Count Processing

  30. PFDPU Integration and Test • PFDPU integration per • MAVEN-PF-TP-003 tested: • Safe-to-Mate • Command Test • Telemetry Test • Power In-Rush Test DCB LVPS Analyzer

  31. Mechanical Fit-Check Fit Check with Mechanical Chassis

  32. Electronic Parts • Electronic Part Status: • Flight BOMs provided to Parts Engineer • Active parts provided by GSFC • With very little exception, flight active parts being used on EM • UCB Part Stress Analysis (Digital Board, LVPS), using GSFC spreadsheet: • All capacitors, resistors and microcircuits derating guidelines at maximum voltage • CDR capacitors are rated at 50V, which does not meet the requirement to use 100V rating for low voltage applications, requires additional part lot testing • Have not completed spreadsheets for diodes, connectors, transistors • IRAP Part Stress Analysis (Anode, Amplifier, HV): • Anode Board: Complete except for one resistor, waiting for manufacturer info • Amplifiers Board: Not done yet , but no concerns as it is 100% identical to STEREO • HV Board: 90% completed. Minor exceedances on derating: • C12 (capacitor/MCP HVPS): 3kV allowed, 2.8 to 3.15kV applied • C41 (capacitor/ HVNR): 30V allowed, 35V applied • C24 & C25 (capacitor/ HVNR): 6V allowed, 6.7V applied • D21, D22, D42, D43 (diodes): 56V allowed, 60V applied • D44 (diode): may have surge current concern, need simulation to check • D2, D10, D33 (diodes): 2250V allowed (reverse voltage), 2325V applied

  33. SWEA Front-End Electronics (IRAP) • HVPS Board • High Voltage generation (2 kV) • 2kV for deflectors & analyzer • 3.5 kV for MCPs • Voltage Scanning functions • Amplifier Board • Charge amplifiers (A111F) • HV Coupling Board • Interface between high/low voltage functions • Collecting Anodes & Mechanical support for MCPs FM Amplifier Board All FM front-end boards currently in test.

  34. SWEA FM Front-End Electronics (IRAP) HV Coupling Board HV Board (all boards 11.2 cm diameter)

  35. HVPS Board Changes (STEREO  MAVEN) Voltage ranges for Commands and Housekeeping were changed from Stereo Need to adapt some resistor values Values have been calculated and will be confirmed and adjusted (if necessary) by tests Increase Maximum Deflection Potential from 1.5 kV to 1.8 kV Review of transformer design to avoid saturation at 1.8kV Now able to supply 2kV

  36. HV Coupling Board Improvements • On Stereo: Crack problems during soldering of vertical capacitors • Caused by excessive temperature gradient (pads too big) • Solution: Apply solder at each corner and stick that remains PCB and capacitors warmed to 70 C before soldering

  37. SWEA Resources • Front-End Electronics Measured values from STEREO flight unit • Digital Electronics Measured: ~ 70mW • ETU FPGA only 6mA on 2.5V (15mW) • Flight FPGA power will be ~ 3x this • Calculated power using RT54SX72 power calculator for expected utilization is ~ 50mW • Expected utilization < 75% • Power slightly less than PDR estimate (1074mW)

  38. SWEA Mechanical Paul Turin June 15, 2010

  39. Exploded View SWEA detector head Purge port (fitting TBD) LVPS Pedestal housing Digital board Board mounted SC harness and enable connectors Cover HV enable plug

  40. Baseplate Mounting holes (4) Vent port (screened for EMC) Balance mass opening HV Enable plug (green tag item) SC harness connector

  41. SWEA EM on Pedestal EM

  42. Mechanical Changes from PDR • Feet changed to reverse fasteners to thread into boom • Purge fitting clocked 25 deg to improve access to connectors

  43. Margins First mode 197Hz

  44. SWEA Design Loads

  45. Key Mechanical Changes • Scallop inner and outer hemispheres and top cap • Suppress secondary electron signal by factor of 3. • Change coating of top cap from Nuflon to Cu2S • Avoid charging anomaly seen on STEREO. • Metalize backs of deflectors and reduce area of exposed insulators (grid washers) • Minimize areas inside the analyzer that can become charged. • Change positions of deflectors • Better deflection with flatter response.

  46. Surface Coatings 10 cm upper deflector toroidal grid top cover • Black Nickel: • Conducting • Non-magnetic • High emissivity • Survives atomic O SWEA parts plated with high-P electroless black-Ni

  47. SWEA EM Cal Chamber Testing • Calibration utilizes a GSE that controls the instrument, the electron source, and the 3-axis manipulator, and records the data • End-to-end testing: Analyzer  front-end electronics  digital electronics  data products • Verify analyzer, deflector, and V0 voltage sweeps • Verify commands, data and housekeeping products

  48. SWEA Integration and Test At IRAP

  49. AIT Facilities • Class 1000 clean room for MCPs and detector assembly (IRAP) • New class 100 clean room for Maven and ExoMars AITs • Vacuum chamber storage for Maven and ExoMars parts or sub systems. • Heating chamber for Maven and ExoMars hardware sterilization. • Small clean room for electronics gluing and coating (IRAP) • Vacuum chamber and particles beam in class 10K clean room • Thermal chambers (-60°C to +120°C) – IRAP • Class 100K clean rooms available at sub contractors (Comat, Microtec)

  50. Reference Documents • MAVEN SWEA Performance Assurance Plan • MAVEN SWEA UCB to CESR/IRAP Interface Control Document • MAVEN PFP performance requirement • MAVEN PFDPU to instruments ICD • MAVEN – UCB Mission Assurance Implementation Plan (MAIP) • Maven harness specifications • Maven grounding specifications • Maven latchup LET criteria (tech. Note - UCB)