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This charter outlines how the P1800 Working Group maintains and enhances the SystemVerilog language. The organization approves all LRM changes, manages business aspects, and ensures consistency across committees. The process involves developing proposed content, reviewing proposals, and quarterly delivery of drafts. Key enhancements include real type support in assertions, polymorphic behavior, and improvement in design specifications. The schedule includes technical freeze in October 2011 and final draft release in December 2012. For more information, visit the Working Group website and technical committee websites.
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P1800 SV Charter Maintain and enhance SystemVerilog language
P1800 Organization P1800 WG: Approve all LRM changes Manages the business aspects Champions: Review all LRM changes for language consistency across SV-* committees Technical committees: Enhancements, Errata, and Clarifications SV-AC: Assertions SV-CC: Foreign APIs SV-DC: Analog Connection SV-BC: Design Subset SV-EC: Test benches
P1800 Development Process • Develop proposed content for the next revision • Open meeting to identify key issues from the community at large • Development of proposed project lists by each of the SV-* committees • Approval of the project lists by P1800 WG • Development of LRM changes • Development of proposed LRM changes by SV-* committees • Review of proposals by Champions to ensure consistency, and cross committee communication • Acceptance of individual changes by P1800 WG • Quarterly delivery of drafts incorporating changes to date • Development and review of Ballot Draft • Freeze of work in SV-* committees • Release of review draft • Ballot draft update based on review of review draft by SV-* committees and interested entities • Ballot draft approval by P1800 WG
P1800 Key Enhancements • SV-AC • Real type support in assertions • Output arguments in checkers • Interface formals in checkers • Assertion system functions • Clock inference in sequences • SV-BC • Add parameterized tasks and functions • Improve macro specification • Improve interface ports and virtual interfaces • Improve design specification and elaboration • Enumeration extension • SV-CC • Allow C++ classes and SystemVerilog classes to be shared via DPI • Representation of super and this in VPI • Support for Unified Coverage Interoperability Standard • Improve interaction between DPI and VPI • Create VPI data model extensions for Checkers • SV-EC • Polymorphic behaviour of instantiation • Constraint composition • Legality to assign an interface containing a class declaration to a virtual interface • Aspect Oriented Programming (AOP) features • Dotted names within inlined constraints • SV-DC • Development of a roadmap for enhancements in this area
P1800 Schedule • October, 2010: Officer elections • October 2011: Technical freeze • January 2012: Ballot draft available • July, 2012: Reballot draft available • December, 2012: 1800-2012 available
P1800 SV Roster Voting Members Accellera Cadence Intel Mentor Graphics Oracle Synopsys Freescale Marvel
P1800 SV Contacts Working Group website http://www.eda.org/sv-ieee1800/ http://www.eda.org/twiki/bin/view.cgi/P1800/P1800Agendas Technical committee websites SV-AC (Assertions) http://www.eda.org/twiki/bin/view.cgi/P1800/SystemVerilogAssertionCommittee SV-BC (Design) http://www.eda.org/sv-bc/ SV-CC (VPI) http://www.eda.org/twiki/bin/view.cgi/P1800/SystemVerilogInterfacesCommittee SV-EC (Testbench) http://www.eda.org/sv-ec/ SV-DC (Analog connection) http://www.eda.org/sv-dc/
