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Linux on an FPGA

Linux on an FPGA. Team: Anthony Bentley Dylan Ismari Bryan Myers Tyler Jordan Mario Espinoza Sponsor: Dr. Alonzo Vera. Presentation Overview. Project Description Why it's necessary Milestones Challenges and Concerns Design process Milestones Current Status Deliverables.

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Linux on an FPGA

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  1. Linux on an FPGA Team: Anthony Bentley Dylan Ismari Bryan Myers Tyler Jordan Mario Espinoza Sponsor: Dr. Alonzo Vera

  2. Presentation Overview Project Description Why it's necessary Milestones Challenges and Concerns Design process Milestones Current Status Deliverables

  3. Project Description Get a working Linux kernel running on an FPGA implementing the OpenRISC processor architecture Document the process for reproducibility Create low-level hardware and software modules using the base platform

  4. Why it's necessary The process of loading a Linux kernel onto an FPGA is complicated, time consuming, and not well documented This project will streamline the process and be used as a starting place for further development Contribute to the Open Source community

  5. Team Breakdown Hardware Team: Dylan Ismari, Tyler Jordan, Mario Espinoza In charge of implementing the hardware cores Software Team: Anthony Bentley, Bryan Myers, Mario Espinoza In charge of configuring and loading the kernel, and writing software drivers Team Leader: Anthony Bentley Sponsor: Dr. Alonzo Vera Provides insight, mentorship and previous experience

  6. Technologies Hardware: OpenRISC – opensource processor architecture made available from opencores.org ML505 board – FPGA made by Diligent Xilinx ISE development environment – Environment we will use to develop the hardware specifications Software: OpenRISC development toolchain – GCC configured for OpenRISC, Binutils, uClibc, Busybox, OpenRISC simulator Linux kernel – Pared down and configured for OpenRISC

  7. Challenges and Concerns Inconsistent environments – drivers, software and toolchains Bad documentation Closed-source software

  8. Design Process: Methodology Iterative development – promotes flexibility, easier to debug Divide the design steps into a set of Tiers where Tier 0 is the minimum functionality of the system and Tier 3 has all the desired functionality Design phase for each Tier will include a hardware core, software drivers, and testing/debugging

  9. Design Process: Tier 0 Tier 0 is the absolute minimum needed for a working system Includes OpenRISC CPU configured for the ML505 FPGA RAM UART and wishbone SD-Flash Memory to boot the kernel

  10. Design Process: Tier 0

  11. Design Process: Tier 1 Tier 1 will build VGA and USB cores on top of Tier 0 through the wishbone bus VGA and USB cores are required for our system to interact with devices such as a display and webcam Minimum tier necessary for a demonstration of the project

  12. Design Process: Tier 1

  13. Design Process: Tier 2 Tier 2 of the design implements an ethernet core Ethernet capabilities will allow our system to network with other systems

  14. Design Process: Tier 2

  15. Design Process: Tier 3 Tier 3 will implement SATA hard disk and audio cores Will be implemented as time allows The “icing on the cake” for our system, allows access to mass storage and audio capabilities

  16. Design Process: Tier 3

  17. Milestones Setting up repository and toolchain Running software on OpenRISC simulator Linux demo on physical hardware External hardware modules Software applications and drivers

  18. Current Status Git repository – set up and storing our code and documents Toolchain – installed and working on development computers Next Month: Synthesized CPU core loaded on board Compiling and running our own programs in simulation

  19. Deliverables Documentation – Upstream READMEs and web/wiki pages, full tutorials, requirements document, project timeline and Gantt chart, meeting minutes, and weekly reports Source Code – VHDL and Verilog hardware specifications, C code for drivers and applications Git repository: Stores up-to-date versions of all documentation and source code as well as revision history

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