Advanced Implantation Detector Array (AIDA): Project Summary & Status

1. Advanced Implantation Detector Array (AIDA): Project Summary & Status presented by Tom Davinson on behalf of the AIDA collaboration (Edinburgh – Liverpool – STFC DL & RAL) Tom Davinson School of Physics & Astronomy The University of Edinburgh

2. AIDA Project Project web site http://www.ph.ed.ac.uk/~td/AIDA/welcome.html The University of Edinburgh (lead RO) Phil Woods et al. The University of Liverpool Rob Page et al. STFC DL & RAL John Simpson et al. Project Manager: Tom Davinson Project commenced: September 2006

3. DESPEC: Implantation DSSD Concept • SuperFRS, Low Energy Branch (LEB) • Exotic nuclei – energies ~ 50 – 200MeV/u • Implanted into multi-plane, highly segmented DSSD array • Implant – decay correlations • Multi-GeV DSSD implantation events • Observe subsequent p, 2p, a, b, g, bp, bn … decays • Measure half lives, branching ratios, decay energies … • Tag interesting events for gamma and neutron detector arrays

4. Implantation DSSD Configurations • Two configurations proposed: • 8cm x 24cm • “cocktail” mode • many isotopes measured simultaneously • b) 8cm x 8cm • high efficiency mode • concentrate on particular isotope(s)

5. AIDA: DSSD Array Design courtesy B.Rubio • 8cm x 8cm DSSDs • common wafer design for 8cm x 24cm and 8cm x 8cm configurations • 8cm x 24cm • 3 adjacent wafers – horizontal strips series bonded • 128 p+n junction strips, 128 n+n ohmic strips per wafer • strip pitch 625mm • wafer thickness 1mm • DE, Veto and up to 6 intermediate planes • 4096 channels (8cm x 24cm) • overall package sizes (silicon, PCB, connectors, enclosure … ) • ~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm

6. ASIC Design Requirements Selectable gain 20 100020000 MeV FSR Low noise 12 60050000 keV FWHM energy measurement of implantation and decay events Selectable threshold < 0.25 – 10% FSR observe and measure low energy b, b detection efficiency Integral non-linearity < 0.1% and differential non-linearity < 2% for > 95% FSR spectrum analysis, calibration, threshold determination Autonomous overload detection & recovery ~ ms observe and measure fast implantation – decay correlations Nominal signal processing time < 10ms observe and measure fast decay – decay correlations Receive (transmit) timestamp data correlate events with data from other detector systems Timing trigger for coincidences with other detector systems DAQ rate management, neutron ToF

7. Schematic of Prototype ASIC Functionality • Note – prototype ASIC will also evaluate use of digital signal processing • Potential advantages • decay – decay correlations to ~ 200ns • pulse shape analysis • ballistic deficit correction

8. Prototype AIDA ASIC: Channel Layout • High (20MeV FSR), intermediate (1GeV FSR) and low gain (20GeV FSR) channels in parallel • Blocks are sequenced to follow signal’s flow (“left to right”) • Shaper and peak hold at back end to minimize noise • 400mm x 6mm Peak Holds + MUX Fast comparators High speed buffer Slow comparator 700pF feedback capacitor Shapers Preamplifiers + feedback 400mm ~6mm

9. Prototype AIDA ASIC: Top level design • Analogue inputs left edge • Control/outputs right edge • Power/bias top and bottom • 16 channels per ASIC • Prototypes delivered May 2009 MPW run 100 dies delivered • Functional tests at STFC RAL OK

10. Prototype AIDA ASIC: Analogue input and bias reference

11. Prototype AIDA ASIC: Analogue outputs

12. Prototype AIDA ASIC

13. 1: Medium Energy (ME) + ME Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) Trigger output “Data Ready” signal Variable medium-energy (ME) event followed after 5us by a second fixed ME event: the energy of the first event (11.75pC, 23.5pC, 35.25pC) does not affect the response to the second (11.75pC).

14. 1: Medium Energy (ME) + ME Input signals (voltage step capacitive-coupled) Analog output (peak-hold multiplexed output) Trigger output “Data Ready” signal When the data ready signal is active, the correct value is present at the analogue output (after the hit has been detected and the correct address been fed into the output multiplexer). NB: the test environment is very noisy and that affects the measurements.

15. 2: High Energy (HE) + ME Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) “Range” signal High = high-energy channel active “Data Ready” signal Three high-energy (HE) events (610pC, 430pC, 250pC) followed by a ME event (28.8pC): the initial HE event does not affect the response to the second. [The roll-of of the L-ME channel preamplifier is due to the HE channel amplifier becoming active: the two are effectively in parallel. Note the Range signal changing status after the HE event]

16. 2: High Energy (HE) + ME Preamp buffered output (Low-Medium Energy Channel) Analog output (peak-hold multiplexed output) “Data Ready” signal Although the low-medium energy channel preamp saturates, the correct value is stored and multiplexed to the Analog Output when the “Data Ready” signal is active.

17. 3: High Energy (HE) + ME Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) “Range” signal High = high-energy channel active “Data Ready” signal Fixed high-energy (HE) event (610pC) followed by three ME events (15pC, 30pC, 45pC): the ASIC recovers autonomously from the overload of the L-ME channel and the second event is read correctly.

18. 3: High Energy (HE) + ME Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) “Range” signal High = high-energy channel active “Data Ready” signal Fixed high-energy (HE) event (610pC) followed by three ME events (15pC, 30pC, 45pC): the ASIC recovers autonomously from the overload of the L-ME channel and the second event is read correctly.

19. 3: High Energy (HE) + ME Input signals (voltage step capacitive-coupled) Analog output (peak-hold multiplexed output) “Range” signal High = high-energy channel active “Data Ready” signal First value (constant) given by the High-Energy channel, second by the Medium-Energy channel.

20. Prototype AIDA Mezzanine • 4x AIDA ASICs 64 channels • Design complete • Delivery November 9 20 units

21. Prototype AIDA FEE FPGA, Memory, Gbit Digital readout Multiplex readout Power Supplies Clockdistribution Mezzanine • Design complete • Production complete • 8 units (4x AIDA, 2x DL DDG, 2x LYCCA) • Delivered week commencing 21.9.09

22. Prototype FEE card • Initial tests underway (STFC DL DDG) • - FPGA Virtex 5 configuration • - PowerPC with internal memory & terminal • - DDR2 memory tests • - Gbit ethernet • - ASIC comms and discriminator timing • - Analog buffers & ADCs • - etc

23. FEE Assembly Sequence

24. Prototype AIDA Enclosure • Prototype mechanical design • Based on 8cm x 8cm DSSSD • evaluate prior to design for 24cm x 8cm DSSSD • Compatible with RISING, TAS, 4p neutron detector • 12x 8cm x 8cm DSSSDs • 24x AIDA FEE cards • 3072 channels • Design complete • Mechanical assembly in • progress

25. Prototype AIDA Enclosure • Design drawings (PDF) available • http://www.eng.dl.ac.uk/secure/np-work/AIDA/

26. AIDA Project Timeline • November/December 2009 • Systems integration (ASIC+Mezzanine+FEE) • Bench tests • February 2010 • In-beam tests • March 2010 • Design revisions • April 2010 • ASIC engineering run • FEE production run • June 2010 • Production delivery complete

27. Acknowledgements My thanks to: STFC DL Ian Lazarus, Patrick Coleman-Smith, Jonathan Strachan & Paul Morrall STFC RAL Steve Thomas & Davide Braga Edinburgh Zhong Liu Liverpool Dave Seddon, Sami Rinta-Antila & Rob Page

29. Prototype AIDA FEE:

30. Design Study Conclusions • 4’’ or 6” Si wafer technology? • - integrated polysilicon bias resistors (15MW) • - separate coupling capacitors (require 22nF/200V+) • Radiation damage mitigation measures essential • - detector cooling required • Noise specification (12keV FWHM) … “not unreasonable” • Discriminator • - low threshold (<50keV) – slow, compromised for ID > 100nA • - separate timing discriminator – higher threshold • x1000 overload recovery ~ ms achievable • - depends on input pulse shape • - optimisation requires more information