Current Source & Bias Circuits

1. CSE598A/EE597G Spring 2006 Current Source & Bias Circuits Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Pennsylvania State University

2. Introduction • Required Features of Current Source • High Rout • Wide Operation Range • Constant Current Source • Low PVT (Process, Voltage, Temperature) Sensitivity • Required Features of Bias Circuit • Low Rout • Low PVT Sensitivity

3. Current Source Basic Current Source Wilson Current Mirror Cascode Current Mirror

4. Ideal vs. Actual Current Source

5. Simple NMOS Current Source What’s the bad feature of this?

6. Cascode Current Source What’s the bad feature of this?

7. Basic Current Mirror What’s the bad feature of this?

8. Wilson Current Mirror What’s the drawback of this circuit?

9. Cascode Current Mirror But, it still has limited output swing problem.

10. Wide Swing Cascode Current Mirror

11. Bias Circuits Self Bias Circuits PTAT Bias Circuits Band gap Reference

12. Power Supply Dependency of Current Source Consideration Factors - VDD - Channel Length Modulation - Transistor Mismatch How do we generate Iref independent of the supply voltage?

13. Self Biasing Circuit What’s role of Rs? What’s the advantage of these circuits? What’s the problem of these circuits?

14. Improved Self Biasing Circuit Improved Circuit with Start-up Circuit * This Circuit is practical only if Improved Circuit eliminating Body Effect

15. 0℃ 90℃ M1(Ids) Negative TC Positive TC ZTC (Zero Temperature Coefficient) VDD VDD M1(Vgs) A Simple Temperature Compensation Concept vr0 v M1 R1 1. R1 is a conductor which has positive TC 2. M1 has negative TC below ZTC point (Semiconductor) 3. If we control Vr0 below ZTC point, Vr0 become less sensitive to temperature due to opposite TC of M1 and R1 Self Bias Circuit

16. starter ⓐ ⓑ For Temp. Compensation pmos diode Vext ⓑ vref ⓐ Case Study (I) – Self Bias Circuit in DRAM What’s the drawback of these circuits?

17. vr1 Voltage Buffer ⓐ starter For Temp. Compensation ⓐ Case Study (II) – Self Bias Circuit in DRAM Why does this circuit need the voltage buffer? Why are PMOS current mirrors stacked in the reference bias circuit?

18. VBE Referenced CMOS Self-bias Circuit How do we fabricate BJT in CMOS Process Technology? * Temperature Sensitivity ~ - 4000 ppm/C

19. Realization of pnp BJT in CMOS Technology

20. Vth Referenced CMOS Self-Bias Circuit

21. Thermal Voltage Referenced CMOS Self-Bias Circuit

22. Thermal Voltage Referenced CMOS Self-Bias Circuit * Temp. Sensitivity ~ +3300 ppm/C

23. CMOS Band gap Reference What’s the problem?

24. (cont’d) CMOS Band gap Reference Actual Implementation of CMOS Band Gap Reference

25. Actual Implementation of CMOS Band gap Reference

26. Design Lab. – Self Bias Circuit with Temp. Compensation • Schematics * AMIS 0.5um Tech (a) Basic Schematic (b) actual implementation

27. Design Lab. – Self Bias Circuit with Temp. Compensation • Simulation Results VDD Vr0b Vr0 (a) Vr0 (b)

28. Design Lab. – Self Bias Circuit with Temp. Compensation • Simulation Results – Temp. Compensation 90C 90C 25C 25C (a) (a) -10C -10C (b) (b) Vr0 Current

29. 90C 25C -10C Design Lab. – Self Bias Circuit with Temp. Compensation • Zero Temperature Coefficient Point 0.82V

30. References • Joongho Choi, “CMOS analog IC Design,” IDEC Lecture Note, Mar. 1999. • B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001. • Hongjun Park, “CMOS Analog Integrated Circuits Design,” Sigma Press, 1999.